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Layout and logic techniques for yield and reliability enhancement
Several yield and reliability enhancement techniques have been proposed for the compaction, routing and technology mapping stages of VLSI design. For yield, we modify the existing layouts to reduce the sensitivity of the design to random point defects, which are the main yield detractors in today's IC technology. For reliability, we deal with several important failure mechanisms including electromigration, antenna effect, crosstalk noise and hot-carrier effect.^ At the layout compaction stage, new techniques for yield enhancement are presented and the yield improvement results on some industrial examples are shown. These new techniques take 2D connections into consideration when performing 1D compaction and they consider the problem of data volume control when dealing with hierarchical design. For this stage of the VLSI layout design, we also propose a minimum layout perturbation compaction algorithm for electromigration reliability enhancement. This algorithm can increase the width of the wires which have electromigration reliability problems and resolve the design rule violations introduced by the wire widening process with minimum changes to the layout so that the previously achieved layout optimization goals such as area, performance and yield can be preserved as much as possible.^ At the routing stage, a layer reassignment algorithm is presented for yield enhancement for 2-layer channel routing. This layer reassignment approach is then extended to antenna effect minimization during the 3-layer routing process. We also develope an algorithm which combines layer reassignment, track reassignment and dogleg insertion to reduce the crosstalk noise in routing.^ For the technology mapping stage, a logic level hot-carrier effect model is presented. Based on this model a mapping algorithm which targets hot-carrier effect is proposed and it is shown that a design with the lowest power measure, which has long been regarded as the rough measure of reliability, is not always the best design for reliability.^ Experimental results have shown that by applying the proposed techniques it is possible to achieve significant yield and reliability improvement during the layout and logic levels of VLSI design. ^
Engineering, Electronics and Electrical|Computer Science
Chen, Zhan, "Layout and logic techniques for yield and reliability enhancement" (1998). Doctoral Dissertations Available from Proquest. AAI9841852.