We argue that the road and obstacle geometry are two important factors that should be appropriately addressed when studying the communications throughput of VANETs. To this end we first study the effect of traffic conditions and road geometry on VANET throughput scaling laws. We use graph-theoretic and geometrical concepts to derive the throughput scaling of single roads, downtown grids, and general geometry road systems.

Moreover, since vehicular communications are supposed to operate in the high frequency ranges, line-of-sight between communicating vehicles picks up importance in VANETs. We use computational geometry tools to study how the specific geometry of obstacles (such as buildings) affects the capacity of urban area VANETs.

Finally, the design goal in MANETs is mostly to enhance the communications metrics (such as throughput and/or delay) of the network, whereas in VANETs, is mainly to improve the safety and efficiency of commute. Yet, better performance in terms of the communications metrics does not necessarily lead into improved safety and efficiency of driving. To this end, the main theme of this dissertation is dedicated to the application-oriented design of VANETs for safety applications. To this end we bring the drivers’ application needs to the forefront of our attention and provide an analytic framework for VANET safety application design during both sparse and dense vehicular traffic conditions. We use tools from stochastic geometry to derive the optimal MAC parameters that satisfy the safety requirements of the system and validate our results through NS-2 simulations. Our ultimate goal there is to fill-in the current gap between purely traffic-based studies that fail to account for the non-idealities of communications, and communications-based ones which neglect the application needs of the system.

In this dissertation, we propose to develop an integrated nano-fabric, (broadly defined as nanostructures/devices in conjunction with paradigms for assembly, inter-connection and circuit styles), as opposed to approaches that focus on MOSFET replacement devices as the ultimate goal. In the `fabric-centric' mindset, design choices at individual levels are made compatible with the fabric as a whole and minimize challenges for nanomanufacturing while achieving system-level benefits vs. scaled CMOS.

We present semiconductor nanowire based nano-fabrics incorporating these fabric-centric principles called NASICs and N3ASICs and discuss how we have taken them from initial design to experimental prototype. Manufacturing challenges are mitigated through careful design choices at multiple levels of abstraction. Regular fabrics with limited customization mitigate overlay alignment requirements. Cross-nanowire FET devices and interconnect are assembled together as part of the uniform regular fabric without the need for arbitrary fine-grain interconnection at the nanoscale, routing or device sizing. Unconventional circuit styles are devised that are compatible with regular fabric layouts and eliminate the requirement for using complementary devices.

Core fabric concepts are introduced and validated. Detailed analyses on device-circuit co-design and optimization, cascading, noise and parameter variation are presented. Benchmarking of nanowire processor designs vs. equivalent scaled 16nm CMOS shows up to 22X area, 30X power benefits at comparable performance, and with overlay precision that is achievable with present-day technology. Building on the extensive manufacturing-friendly fabric framework, we present recent experimental efforts and key milestones that have been attained towards realizing a proof-of-concept prototype at dimensions of 30nm and below.