Power-efficient RAM mapping algorithms for FPGA embedded memory blocks

Authors

R Tessier
V Betz
D Neto
A Egier
T Gopalsamy

Publication Date

2007

Journal or Book Title

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

DOI

https://doi.org/10.1109/TCAD.2006.887924

Pages

278-290

Volume

26

Issue

2

Recommended Citation

Tessier, R; Betz, V; Neto, D; Egier, A; and Gopalsamy, T, "Power-efficient RAM mapping algorithms for FPGA embedded memory blocks" (2007). IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. 1075.
https://doi.org/10.1109/TCAD.2006.887924