A Monitor Interconnect and Support Subsystem for Multicore Processors
Publication Date
2009
Journal or Book Title
2009 Design, Automation & Test in Europe Conference & Exhibition
Abstract
In many current SoCs, the architectural interface to on-chip monitors is ad hoc and inefficient. In this paper, a new architectural approach which advocates the use of a separate low-overhead subsystem for monitors is described. A key aspect of this approach is an on-chip interconnect specifically designed for monitor data with different priority levels. The efficiency of our monitor interconnect is assessed for a multicore system using both an interconnect and a system-level simulator. Collected monitor information is used by a dedicated processor to control the frequency and voltage of individual multicore processors. Experimental results show that the new low-overhead subsystem facilitates employment of thermal and delay-aware dynamic voltage and frequency scaling.
DOI
https://doi.org/10.1109/DATE.2009.5090766
Pages
761-766
Book Series Title
Design, Automation and Test in Europe Conference and Expo
Recommended Citation
Madduri, Sailaja; Vadlamani, Ramakrishna; Burleson, Wayne; and Tessier, Russell, "A Monitor Interconnect and Support Subsystem for Multicore Processors" (2009). 2009 Design, Automation & Test in Europe Conference & Exhibition. 116.
https://doi.org/10.1109/DATE.2009.5090766