The effect of placement on yield for standard cell designs

Authors

RK Prasad
I Koren

Publication Date

2000

Journal or Book Title

IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS

DOI

https://doi.org/10.1109/DFTVS.2000.886968

Pages

3-11

Book Series Title

IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS - PROCEEDINGS

Recommended Citation

Prasad, RK and Koren, I, "The effect of placement on yield for standard cell designs" (2000). IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS. 783.
https://doi.org/10.1109/DFTVS.2000.886968