On the effect of floorplanning on the yield of large area integrated circuits
Publication Date
1997
Journal or Book Title
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
DOI
https://doi.org/10.1109/92.555982
Pages
3-14
Volume
5
Issue
1
Recommended Citation
Koren, Z and Koren, I, "On the effect of floorplanning on the yield of large area integrated circuits" (1997). IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 795.
https://doi.org/10.1109/92.555982
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