An Efficient Technique for Leakage Current Estimation in Nanoscaled CMOS Circuits Incorporating Self-Loading Effects

Authors

A Sanyal
A Rastogi
W Chen
S Kundu

Publication Date

2010

Journal or Book Title

IEEE TRANSACTIONS ON COMPUTERS

DOI

https://doi.org/10.1109/TC.2010.75

Pages

922-932

Volume

59

Issue

7

Recommended Citation

Sanyal, A; Rastogi, A; Chen, W; and Kundu, S, "An Efficient Technique for Leakage Current Estimation in Nanoscaled CMOS Circuits Incorporating Self-Loading Effects" (2010). IEEE TRANSACTIONS ON COMPUTERS. 883.
https://doi.org/10.1109/TC.2010.75