Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors
Publication Date
2010
Journal or Book Title
IEEE TRANSACTIONS ON COMPUTERS
DOI
https://doi.org/10.1109/TC.2009.76
Pages
651-665
Volume
59
Issue
5
Recommended Citation
Khan, O and Kundu, S, "Thread Relocation: A Runtime Architecture for Tolerating Hard Errors in Chip Multiprocessors" (2010). IEEE TRANSACTIONS ON COMPUTERS. 887.
https://doi.org/10.1109/TC.2009.76
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