"Core Test Wrapper Design to Reduce Test Application Time for Modular S" by H Yi and S Kundu

Electrical and Computer Engineering Faculty Publication Series

Core Test Wrapper Design to Reduce Test Application Time for Modular SoC Testing

H Yi
S Kundu

2008

412-420

23RD IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT-TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS

IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems

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