On modeling and testing of lithography related open faults in nano-CMOS circuits
Publication Date
2008
Journal or Book Title
2008 DESIGN, AUTOMATION AND TEST IN EUROPE, VOLS 1-3
DOI
https://doi.org/10.1109/DATE.2008.4484745
Pages
533-538
Book Series Title
Design, Automation and Test in Europe Conference and Expo
Recommended Citation
Sreedhar, A; Sanyal, A; and Kundu, S, "On modeling and testing of lithography related open faults in nano-CMOS circuits" (2008). 2008 DESIGN, AUTOMATION AND TEST IN EUROPE, VOLS 1-3. 906.
https://doi.org/10.1109/DATE.2008.4484745
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