An efficient technique for leakage current estimation in sub 65nm scaled CMOS circuits based on loading effect

Authors

A Rastogi
W Chen
A Sanyal
S Kundu

Publication Date

2007

Journal or Book Title

20TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS

DOI

https://doi.org/10.1109/VLSID.2007.32

Pages

583-588

Book Series Title

International Conference on VLSI Design, Proceedings

Recommended Citation

Rastogi, A; Chen, W; Sanyal, A; and Kundu, S, "An efficient technique for leakage current estimation in sub 65nm scaled CMOS circuits based on loading effect" (2007). 20TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS. 918.
https://doi.org/10.1109/VLSID.2007.32