Electrical & Computer Engineering Masters Theses Collection

Benchmarking Virtual Network Mapping Algorithms

Zhu, Jin — Fri, 23 Nov 2012 07:59:11 PST

The network architecture of the current Internet cannot accommodate the deployment of novel network-layer protocols. To address this fundamental problem, network virtualization has been proposed, where a single physical infrastructure is shared among different virtual network slices. A key operational problem in network virtualization is the need to allocate physical node and link resources to virtual network requests. While several different virtual network mapping algorithms have been proposed in literature, it is difficult to compare their performance due to differences in the evaluation methods used. In this thesis work, we proposed VNMBench, a virtual network mapping benchmark that provides a set of standardized inputs and evaluation metrics. Using this benchmark, different algorithms can be evaluated and compared objectively. The benchmark model separate into two parts: static model and dynamic model, which operated in fixed and changed mapping process. We present such an evaluation using three existing virtual network mapping algorithms. We compare the evaluation results of our synthetic benchmark with those of actual Emulab requests to show that VNMBench is sufficiently realistic. We believe this work provides an important foundation to quantitatively evaluating the performance of a critical component in the operation of virtual networks.

Large Scale Image Retrieval From Books

Zhao, Mao — Fri, 23 Nov 2012 07:59:09 PST

Search engines play a very important role in daily life. As multimedia product becomes more and more popular, people have developed search engines for images and videos. In the first part of this thesis, I propose a prototype of a book image search engine. I discuss tag representation for the book images, as well as the way to apply the probabilistic model to generate image tags. Then I propose the random walk refinement method using tag similarity graph. The image search system is built on the Galago search engine developed in UMASS CIIR lab.

Consider the large amount of data the search engines need to process, I bring in cloud environment for the large-scale distributed computing in the second part of this thesis. I discuss two models, one is the MapReduce model, which is currently one of the most popular technologies in the IT industry, and the other one is the Maiter model. The asynchronous accumulative update mechanism of Maiter model is a great fit for the random walk refinement process, which takes up 84% of the entire run time, and it accelerates the refinement process by 46 times.

Terahertz Imaging for Cancer Detection

St. Peter, Benjamin A. — Fri, 23 Nov 2012 07:53:00 PST

This project evaluates the ability of terahertz (THz) radiation to differentiate cancerous from non-cancerous human breast lumpectomy and mastectomy tissue. This is done by aiming a narrow-band THz beam at medical samples and measuring reflected power. THz images of specimens from Breast Conservation Surgery (BCS) were created using a gas laser source and mechanical scanning. The design and characterization of this system is discussed in detail. The images were correlated with optical histological micrographs of the same specimens and discrimination values of more than 70% were found for five of the six samples using Receiver Operating Characteristic (ROC) analysis.

Reformulation of the Muffin-Tin Problem in Electronic Structure Calculations within the FEAST Framework

Levin, Alan R. — Fri, 23 Nov 2012 07:24:29 PST

This thesis describes an accurate and scalable computational method designed to perform nanoelectronic structure calculations. Built around the FEAST framework, this method directly addresses the nonlinear eigenvalue problem. The new approach allows us to bypass traditional approximation techniques typically used for first-principle calculations. As a result, this method is able to take advantage of standard muffin-tin type domain decomposition techniques without being hindered by their perceived limitations. In addition to increased accuracy, this method also has the potential to take advantage of parallel processing for increased scalability.

The Introduction presents the motivation behind the proposed method and gives an overview of what will be presented for this thesis. Chapter 1 explains how electronic structure calculations are currently performed, including an overview of Density Functional Theory and the advantages and disadvantages of various numerical techniques. Chapter 2 describes, in detail, the method proposed for this thesis, including mathematical justification, a matrix-level example, and a description of implementing the FEAST algorithm. Chapter 3 presents and discusses results from numerical experiments for Hydrogen and various Hydrogen molecules, Methane, Ethane, and Benzene. Chapter 4 concludes with a summary of the presented work and its impact in the field.

Heterogeneous Graphene Nanoribbon-CMOS Multi-State Volatile Random Access Memory Fabric

Khasanvis, Santosh — Fri, 23 Nov 2012 07:23:53 PST

CMOS SRAM area scaling is slowing down due to several challenges faced by transistors at nanoscale such as increased leakage. This calls for new concepts and technologies to overcome CMOS scaling limitations. In this thesis, we propose a multi-state memory to store multiple bits in a single cell, enabled by graphene and graphene nanoribbon crossbar devices (xGNR). This could provide a new dimension for scaling. We present a new multi-state volatile memory fabric called Graphene Nanoribbon Tunneling Random Access Memory (GNTRAM) featuring a heterogeneous integration between graphene and CMOS. A latch based on the xGNR devices is used as the memory element which exhibits 3 stable states. We propose binary and ternary GNTRAM and compare them with respect to 16nm CMOS SRAM and 3T DRAM. Ternary GNTRAM (1.58 bits/cell) shows up to 1.77x density-per-bit benefit over CMOS SRAMs and 1.42x benefit over 3T DRAM in 16nm technology node. Ternary GNTRAM is also up to 1196x more power-efficient per bit against high-performance CMOS SRAMs during stand-by.

To enable further scaling, we explore two approaches to increase the number of bits per cell. We propose quaternary GNTRAM (2 bits/cell) using these approaches and extensively benchmark these designs. The first uses additional xGNR devices in the latch to achieve 4 stable states and the quaternary memory shows up to 2.27x density benefit vs. 16nm CMOS SRAMs and 1.8x vs. 3T DRAM. It has comparable read performance in addition to being power-efficient, up to 1.32x during active period and 818x during stand-by against high performance SRAMs. However, the need for relatively high-voltage operation may ultimately limit this scaling approach. An alternative approach is also explored by increasing the stub length in the xGNR devices, which allows for storing 2 bits per cell without requiring an increased operating voltage. This approach for quaternary GNTRAM shows higher benefits in terms of power, specifically up to 4.67x in terms of active power and 3498x during stand-by against high-performance SRAMs.

Multi-bit GNTRAM has the potential to realize high-density low-power nanoscale memories. Further improvements may be possible by using graphene more extensively, as graphene transistors become available in future.

A Theoretical Approach to Fault Analysis and Mitigation in Nanoscale Fabrics

Khan, Md Muwyid Uzzaman — Fri, 23 Nov 2012 07:23:46 PST

High defect rates are associated with novel nanodevice-based systems owing to unconventional and self-assembly based manufacturing processes. Furthermore, in emerging nanosystems, fault mechanisms and distributions may be very different from CMOS due to unique physical layer aspects, and emerging circuit and logic styles. Thus, theoretical fault models for nanosystems are necessary to extract detailed characteristics of fault generation and propagation. Using the intuition garnered from the theoretical analysis, modular and structural redundancy schemes can be specifically tailored to the intricacies of the fabric in order to achieve higher reliability of output signals.

In this thesis, we develop a detailed analytical fault model for the Nanoscale Application Specific Integrated Circuits (NASIC) fabric that can determine probabilities of output faults taking into account the defect scenarios, the logic and circuit style of the fabric as well as structural redundancy schemes that may be incorporated in the circuits. Evaluation of fault rates using the analytical model for single NASIC tiles show an inequality of the probability of output faulty ‘1’s and ‘0’s. To mitigate the effects of the unequal fault rates, biased voting schemes are introduced and are shown to achieve up to 27% improvement in the reliability of output signals compared to conventional majority voting schemes.

NASIC circuits have to be cascaded in order to build larger systems. Furthermore, modular redundancy alone will be insufficient to tolerate high defect rates since multiple input modules may be faulty. Hence incorporation of structural redundancy is crucial. Thus in this thesis, we study the propagation of faults through a cascade of NASIC circuits employing the conventional structural redundancy scheme which is referred to here as the Regular Structural Redundancy. In our analysis we find that although circuits with Regular Structural Redundancy achieve greater signal reliability compared to non-redundant circuits, the signal reliability rapidly drops along the cascade due to an escalation of faulty ‘0’s. This effect is attributed to the poor tolerance of input faulty ‘0’s exhibited by circuits with the Regular Structural Redundancy. Having identified this, we design a new scheme called the Staggered Structural Redundancy prioritizing the tolerance of input faulty ‘0’s. A cascade of circuits employing the Staggered Structural Redundancy is shown to maintain signal reliability greater than 0.98 for over 100 levels of cascade at 5% defect rate whereas the signal reliability for a cascade of circuits with the Regular Structural Redundancy dropped to 0.5 after 7 levels of cascade.

Techniques for Detection of Malicious Packet Drops in Networks

Desai, Vikram R. — Fri, 23 Nov 2012 07:10:15 PST

The introduction of programmability and dynamic protocol deployment in routers, there would be an increase in the potential vulnerabilities and attacks . The next- generation Internet promises to provide a fundamental shift in the underlying architecture to support dynamic deployment of network protocols. In this thesis, we consider the problem of detecting malicious packet drops in routers. Specifically, we focus on an attack scenario, where a router selectively drops packets destined for another node. Detecting such an attack is challenging since it requires differentiating malicious packet drops from congestion-based packet losses. We propose a controller- based malicious packet detection technique that effectively detects malicious routers using delayed sampling technique and verification of the evidence. The verification involves periodically determining congestion losses in the network and comparing the forwarding behaviors of the adjoining routers to affirm the state of a router in the network. We provide a performance analysis of the detection accuracy and quantify the communication overhead of our system. Our results show that our technique provides accurate detection with low performance overhead.

THE RADIATION QUALITY FACTOR OF VERTICALLY POLARIZED SPHERICAL ANTENNAS ABOVE A CONDUCTING GROUND PLANE

Chang, Hsieh-Chi — Fri, 23 Nov 2012 07:05:38 PST

The radiation quality factor of small vertically polarized antennas above a ground plane is investigated. Although the quality factor of small antennas in free space has been investigated extensively in the past, the exact effect of a conducting ground plane on the antenna bandwidth is not clearly understood. In this thesis, quality factors of vertically polarized antennas above a ground plane are computed and compared with their free-space counterparts. The theoretical results on quality factors are validated with simulations of electrically small spherical helix antennas.

Towards Logic Functions as the Device using Spin Wave Functions Nanofabric

Shabadi, Prasad — Thu, 23 Aug 2012 05:59:31 PDT

As CMOS technology scaling is fast approaching its fundamental limits, several new nano-electronic devices have been proposed as possible alternatives to MOSFETs. Research on emerging devices mainly focusses on improving the intrinsic characteristics of these single devices keeping the overall integration approach fairly conventional. However, due to high logic complexity and wiring requirements, the overall system-level power, performance and area do not scale proportional to that of individual devices.

Thereby, we propose a fundamental shift in mindset, to make the devices themselves more functional than simple switches. Our goal in this thesis is to develop a new nanoscale fabric paradigm that enables realization of arbitrary logic functions (with high fan-in/fan-out) more efficiently. We leverage on non-equilibrium spin wave physical phenomenon and wave interference to realize these elementary functions called Spin Wave Functions (SPWFs).

In the proposed fabric, computation is based on the principle of wave superposition. Information is encoded both in the phase and amplitude of spin waves; thereby providing an opportunity for compressed data representation. Moreover, spin wave propagation does not involve any physical movement of charge particles. This provides a fundamental advantage over conventional charge based electronics and opens new horizons for novel nano-scale architectures.

We show several variants of the SPWFs based on topology, signal weights, control inputs and wave frequencies. SPWF based designs of arithmetic circuits like adders and parallel counters are presented. Our efforts towards developing new architectures using SPWFs places strong emphasis on integrated fabric-circuit exploration methodology. With different topologies and circuit styles we have explored how capabilities at individual fabric components level can affect design and vice versa. Our estimates on benefits vs. 45nm CMOS implementation show that, for a 1-bit adder, up to 40x reduction in area and 228x reduction in power is possible. For the 2-bit adder, results show that up to 33x area reduction and 222x reduction in power may be possible.

Building large scale SPWF-based systems, requires mechanisms for synchronization and data streaming. In this thesis, we present data streaming approaches based on Asynchronous SPWFs (A-SPWFs). As an example, a 32-bit Carry Completion Sensing Adder (CCSA) is shown based on the A-SPWF approach with preliminary power, performance and area evaluations.

The Measurement of Internal Temperature Anomalies in the Body Using Microwave Radiometry and Anatomical Information: Inference Methods and Error Models

Sobers, Tamara V. — Thu, 23 Aug 2012 05:59:28 PDT

The ability to observe temperature variations inside the human body may help in detecting the presence of medical anomalies. Abnormal changes in physiological parameters (such as metabolic and blood perfusion rates) cause localized tissue temperature change. If the anatomical information of an observed tissue region is known, then a nominal temperature profile can be created using the nominal physiological parameters. Temperature-varying radiation emitted from the human body can be captured using microwave radiometry and compared to the expected radiation from nominal temperature profiles to detect anomalies. Microwave radiometry is a passive system with the ability to capture radiation from tissue up to several centimeters deep into the body. Our proposed method is to use microwave radiometry in conjunction with another imaging modality (such as ultrasound) that can provide the anatomical information needed to generate nominal profiles and improve detection of temperature anomalies. An inference framework is developed for using the nominal temperature profiles and radiometric weighting functions obtained from electromagnetic simulation software, to detect and estimate the location of temperature anomalies. The effects on inference performance of random and systematic deviations from nominal tissue parameter values in normal tissue are discussed and analyzed.