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Document Type

Campus Access

Degree Program

Electrical & Computer Engineering

Degree Type

Master of Science in Electrical and Computer Engineering (M.S.E.C.E.)

Year Degree Awarded

2013

Month Degree Awarded

May

Keywords

CMOS Imager, A/D Converter, SAR

Abstract

The ever-increasing resolution of CMOS imagers has steadily driven the requirements of readout circuitry. As the number of sensors on a chip increases, the bandwidth of the readout circuit must be increased correspondingly to maintain a constant frame rate. Column parallel A/D converters are commonly used to divide the conversions among many converters. However, implementing high-speed, high-resolution A/D converters at the column level is challenging because the entire circuit needs to be as narrow as the sensor.

This thesis presents the design of a 10-bit, one million conversions per second column-parallel A/D converter. A factor of four increase in speed over conventional converters was achieved by combining techniques of successive approximation and two-step subranging in a distributed column-parallel architecture. The speed of the converter makes it suitable to be integrated with a 1-megapixel sensor array providing a frame rate at 1000fps with 11µm pixels in a 0.35µm CMOS technology.

First Advisor

Christopher Salthouse

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