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ON-CHIP THERMAL SENSING IN DEEP SUB-MICRON CMOS
Document Type: Open Access
Degree Program
Electrical & Computer Engineering
Degree Type
Master of Science in Electrical and Computer Engineering (M.S.E.C.E.)
Year Degree Awarded
2007
Month Degree Awarded
September
Primary Subject Category
Electrical engineering
Secondary Subject Category
Computer science; Electrical engineering; Engineering
Keywords
Thermal Sensor, Process variations, Supply noise, Power, Interconnect, Oscillator
Advisor(s) or Committee Chair
BURLESON, WAYNE P
Abstract
ON-CHIP THERMAL SENSING IN DEEP SUB-MICRON CMOS
August 2007
BASAB DATTA
B.S., G.G.S. INDRAPRASTHA UNIVERSITY, NEW DELHI
M.S.E.C.E, UNIVERSITY OF MASSACHUSETTS AMHERST
Directed by: Professor Wayne P. Burleson
Aggressive technology scaling and an increasing demand for high performance VLSI circuits has resulted in higher current densities in the interconnect lines and increasingly higher power dissipation in the substrate. Because a significant fraction of this power is converted to heat, an exponential rise in heat density is also experienced. Different activities and sleep modes of the functional blocks in high performance chips cause significant temperature gradients in the substrate and this can be expected to further increase in the GHz frequency regime. The above scenario motivates the need for a large number of lightweight, robust and power-efficient thermal sensors for accurate thermal mapping and thermal management.
We propose the use of Differential Ring Oscillators (DRO) for thermal sensing at the substrate level, utilizing the temperature dependence of the oscillation frequency. They are widely used in current VLSI for frequency synthesis and on-die process characterization; hence provide scope of reusability in design. The DRO oscillation frequency decreases linearly with increase in temperature due to the decrease in current in the signal paths. In current starved inverter topology using the 45nm technology node, the DRO based thermal sensor has a resolution of 2°C and a low active power consumption of 25µW, which can be reduced further by 60-80% by power-gating the design.
Current thermal scaling trends in multilevel low-k interconnect structures suggest an increasing heat density as we move from substrate to higher metal levels. Thus, the deterioration of interconnect performance at extreme temperatures has the capability to offset the degradation in device performance when operating at higher than normal temperatures. We propose using lower-level metal interconnects to perform the thermal sensing. A resolution of ~5°C is achievable for both horizontal and vertical gradient estimation (using current generation time-digitizers).
The time-digitization unit is an essential component needed to perform interconnect based thermal sensing in deep nanometer designs but it adds area and power overhead to the sensor design and limits the resolution of the wire-based sensor. We propose a novel sensor design that alleviates complexities associated with time-to-digital conversion in wire-based thermal sensing. The IBOTS or Interconnect Based Oscillator for Thermal Sensing makes use of wire-segments between individual stages of a ring-oscillator to perform thermal sensing using the oscillator frequency value as the mapping to corresponding wire temperature. The frequency output can be used to generate a digital code by interfacing the IBOTS with a digital counter. In 45nm technology, it is capable of providing a resolution of 1°C while consuming an active power of 250-360µW.
Recommended Citation
Datta, Basab, "ON-CHIP THERMAL SENSING IN DEEP SUB-MICRON CMOS" (2007). Masters Theses. Paper 52.
http://scholarworks.umass.edu/theses/52
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