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Electrical & Computer Engineering
Master of Science (M.S.)
Year Degree Awarded
Month Degree Awarded
Power Amplifier, FPGA, Nios 2, linearization, pade chebyshev, QR decomposition
The emphasis on higher data rates, spectral efficiency and cost reduction has driven the field towards linear modulation techniques such as quadrature phase shift keying (QPSK), quadrature amplitude modulation (QAM), wideband code division multiple access (WCDMA), and orthogonal frequency division multiplexing (OFDM). The result is a complex signal with a non-constant envelope and a high peak-to-average power ratio. This characteristic makes these signals particularly sensitive to the intrinsic nonlinearity of the RF power amplifier (PA) in the transmitter. The nonlinearity will generate intermodulation (IMD) components, also referred to as out-of-band emission or spectral re-growth, which interfere with adjacent channels. Such distortion, or so called Adjacent Channel Interference (ACI), is strictly limited by FCC and ETSI regulations. Meanwhile, the nonlinearity also causes in-band distortion which degrades the bit error rate performance. Typically, the required linearity can be achieved either by reducing power efficiency or by using linearization techniques. For a Class-A PA, simply “backing off” the input power level can improve linearity; however, for high peak to average power ration (PAPR) signals, this normally reduces the power efficiency down to 10% while increasing heat dissipation up to 90%.When considering the vast number of base stations that wireless operators need to account for, increasing power consumption, or in other words, power back-off is not a viable tradeoff. Therefore, amplifier linearization has become an important technology and a desirable alternative to backing-off an amplifier in modern communications systems. In this work, a novel adaptive algorithm is presented for predistorter linearization of power amplifiers. This algorithm uses Pade-Chebyshev polynomials and a QR decomposition followed by back substitution to find the pre-distorter coefficients.This algorithm is implemented on a Field Programmable Gate Array (Stratix 1S80).The implementation provides improved linearization and also runs the algorithm fast enough so that the adaptive part can be done quickly. Yet another challenge was the integration of a transmitter, receiver and this adaptive algorithm into a single FPGA chip and its communication with a base station. The work thus presents a novel pre-distortion implementation technique using an FPGA and a soft processor (Nios 2) which provides significant intermodulation distortion suppression.
Advisor(s) or Committee Chair