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Publication Management of Target-Tracking Sensor Networks(2009-09) Hadi, KhaledTarget tracking has emerged as an important application of sensor networks. There are two subproblems inherent to target tracking. The first is the initial location of the target as it enters the region being covered. The second is following its track once it has been discovered. In this work, we outline an approach to target tracking. We present an energy-aware tracking algorithm that predicts the target track and activates nodes based on that prediction. We then discuss different energy management schemes that resolve tradeoffs between energy savings and track quality for a specified mission lifetime. Our energy management schemes perform better in terms of track quality and have an energy consumption similar to other schemes. We also consider energy harvesting in this energy management. We present a multitarget tracking algorithm; in connection with that, we present a filtering algorithm that improves the quality of tracking. We also study adaptive approaches to manage the tracking process to the observed mobility characteristics of the target. Such adaptive approaches are shown to have noticeable performance advantages.Publication Online Management of Resilient and Power Efficient Multicore Processors(2013-09) Rodrigues, RanceThe semiconductor industry has been driven by Moore's law for almost half a century. Miniaturization of device size has allowed more transistors to be packed into a smaller area while the improved transistor performance has resulted in a significant increase in frequency. Increased density of devices and rising frequency led, unfortunately, to a power density problem which became an obstacle to further integration. The processor industry responded to this problem by lowering processor frequency and integrating multiple processor cores on a die, choosing to focus on Thread Level Parallelism (TLP) for performance instead of traditional Instruction Level Parallelism (ILP). While continued scaling of devices have provided unprecedented integration, it has also unfortunately led to a few serious problems: The first problem is that of increasing rates of system failures due to soft errors and aging defects. Soft errors are caused by ionizing radiations that originate from radioactive contaminants or secondary release of charged particles from cosmic neutrons. Ionizing radiations may charge/discharge a storage node causing bit flips which may result in a system failure. In this dissertation, we propose solutions for online detection of such errors in microprocessors. A small and functionally limited core called the Sentry Core (SC) is added to the multicore. It monitors operation of the functional cores in the multicore and whenever deemed necessary, it opportunistically initiates Dual Modular redundancy (DMR) to test the operation of the cores in the multicore. This scheme thus allows detection of potential core failure and comes at a small hardware overhead. In addition to detection of soft errors, this solution is also capable of detecting errors introduced by device aging that results in failure of operation. The solution is further extended to verify cache coherence transactions. A second problem we address in this dissertation relate to power concerns. While the multicore solution addresses the power density problem, overall power dissipation is still limited by packaging and cooling technologies. This limits the number of cores that can be integrated for a given package specification. One way to improve performance within this constraint is to reduce power dissipation of individual cores without sacrificing system performance. There have been prior solutions to achieve this objective that involve Dynamic Voltage and Frequency Scaling (DVFS) and the use of sleep states. DVFS and sleep states take advantage of coarse grain variation in demand for computation. In this dissertation, we propose techniques to maximize performance-per-power of multicores at a fine grained time scale. We propose multiple alternative architectures to attain this goal. One of such architectures we explore is Asymmetric Multicore Processors (AMPs). AMPs have been shown to outperform the symmetric ones in terms of performance and Performance-per-Watt for a fixed resource and power budget. However, effectiveness of these architectures depends on accurate thread-to-core scheduling. To address this problem, we propose online thread scheduling solutions responding to changing computational requirements of the threads. Another solution we consider is for Symmetric Multicore processors (SMPs). Here we target sharing of the large and underutilized resources between pairs of cores. While such architectures have been explored in the past, the evaluations were incomplete. Due to sharing, sometimes the shared resource is a bottleneck resulting in significant performance loss. To mitigate such loss, we propose the Dynamic Voltage and Frequency Boosting (DVFB) of the shared resources. This solution is found to significantly mitigate performance loss in times of contention. We also explore in this dissertation, performance-per-Watt improvement of individual cores in a multicore. This is based on dynamic reconfiguration of individual cores to run them alternately in out-of-order (OOO) and in-order (InO) modes adapting dynamically to workload characteristics. This solution is found to significantly improve power efficiency without compromising overall performance. Thus, in this dissertation we propose solutions for several important problems to facilitate continued scaling of processors. Specifically, we address challenges in the area of reliability of computation and propose low power design solutions to address power constraints.Publication Hybrid Radio Frequency and Video Framework for Identity-Aware Augmented Perception in Disaster Management and Assistive Technologies(2013-09) Yu, XunyiIn this dissertation, we introduce a hybrid radio frequency and video framework that enables identity aware-augmented perception. Identity-aware augmented perception enhances users' perception of the surrounding by collecting and analyzing information pertaining to each identifiable or tractable target nearby aggregated from various sensors, and presents it visually or audibly augmenting users' own sensory perceptions. We target two application areas of disaster management and assistive technologies. Incident commanders and first responders can use the technology to perceive information specific to a victim, e.g. triage level, critical conditions, visually superimposed on third person or first person video. The blind and visually impaired can use the technology to perceive the direction and distance of static landmarks and moving people nearby, and target specific information, e.g. a store's name and opening hours, a friend's status on social networks. Identifying who is who in video is an important yet challenging problem that can greatly benefit existing video analytics and augmented reality applications. Identity information can be used to improve the presentation of target information on graphical user interface, enable role-based target analytics over long term, and achieve more efficient and accurate surveillance video indexing and querying. Instead of relying on target appearance, we propose a hybrid approach that combines complimentary radio frequency (RF) signal with video to identify targets. Recovering target identities in video using RF is not only useful in its own right, but also provides an alternative formulation that helps to solve difficult problems in individual video and RF domains, e.g., persistent video tracking, accurate target localization using RF signal, anchorless target localization, multi-camera target association, automatic RF and video calibration. We provide a comprehensive RF and video fusion framework to enable identity-aware augmented perception in a variety of scenarios. We propose a two stage data fusion scheme based on tracklets, and formulate the tracklet identification problem under different RF and camera measurement models using network flow or graphical model. We first start from a basic calibrated single fixed camera, fixed RF readers configuration. Then we consider anchorless target identification using pair-wise measurements between mobile RF devices to reduce deployment complexity. Then we incorporate multiple cameras, to improve coverage, camera deployment flexibility, identification accuracy and enable multi-view augmented perception. We propose a self-calibrating identification algorithm, that simplifies manual calibration and improve identification accuracy in environments with obstruction. Finally, we solve the problem of annotating video taken by mobile cameras to provide first-person perception, taking advantage of target appearance, location and identity given by the fixed video hybrid system.Publication Reconfigurable Technologies for Next Generation Internet and Cluster Computing(2013-09) Unnikrishnan, Deepak C.Modern web applications are marked by distinct networking and computing characteristics. As applications evolve, they continue to operate over a large monolithic framework of networking and computing equipment built from general-purpose microprocessors and Application Specific Integrated Circuits (ASICs) that offers few architectural choices. This dissertation presents techniques to diversify the next-generation Internet infrastructure by integrating Field-programmable Gate Arrays (FPGAs), a class of reconfigurable integrated circuits, with general-purpose microprocessor-based techniques. Specifically, our solutions are demonstrated in the context of two applications - network virtualization and distributed cluster computing. Network virtualization enables the physical network infrastructure to be shared among several logical networks to run diverse protocols and differentiated services. The design of a good network virtualization platform is challenging because the physical networking substrate must scale to support several isolated virtual networks with high packet forwarding rates and offer sufficient flexibility to customize networking features. The first major contribution of this dissertation is a novel high performance heterogeneous network virtualization system that integrates FPGAs and general-purpose CPUs. Salient features of this architecture include the ability to scale the number of virtual networks in an FPGA using existing software-based network virtualization techniques, the ability to map virtual networks to a combination of hardware and software resources on demand, and the ability to use off-chip memory resources to scale virtual router features. Partial-reconfiguration has been exploited to dynamically customize virtual networking parameters. An open software framework to describe virtual networking features using a hardware-agnostic language has been developed. Evaluation of our system using a NetFPGA card demonstrates one to two orders of improved throughput over state-of-the-art network virtualization techniques. The demand for greater computing capacity grows as web applications scale. In state-of-the-art systems, an application is scaled by parallelizing the computation on a pool of commodity hardware machines using distributed computing frameworks. Although this technique is useful, it is inefficient because the sequential nature of execution in general-purpose processors does not suit all workloads equally well. Iterative algorithms form a pervasive class of web and data mining algorithms that are poorly executed on general purpose processors due to the presence of strict synchronization barriers in distributed cluster frameworks. This dissertation presents Maestro, a heterogeneous distributed computing framework that demonstrates how FPGAs can break down such synchronization barriers using asynchronous accumulative updates. These updates allow for the accumulation of intermediate results for numerous data points without the need for iteration-based barriers. The benefits of a heterogeneous cluster are illustrated by executing a general-class of iterative algorithms on a cluster of commodity CPUs and FPGAs. Computation is dynamically prioritized to accelerate algorithm convergence. We implement a general-class of three iterative algorithms on a cluster of four FPGAs. A speedup of 7× is achieved over an implementation of asynchronous accumulative updates on a general-purpose CPU. The system offers 154× speedup versus a standard Hadoop-based CPU-workstation cluster. Improved performance is achieved by clusters of FPGAs.Publication Techniques to Increase Computational Efficiency in Some Deterministic and Random Electromagnetic Propagation Problems(2013-09) Ozbayat, SelmanEfficient computation in deterministic and uncertain electromagnetic propagation environments, tackled by parabolic equation methods, is the subject of interest of this dissertation. Our work is comprised of two parts. In the first part we determine efficient absorbing boundary conditions for propagation over deterministic terrain and in the second part we study techniques for efficient quantification of random parameters/outputs in volume and surface based electromagnetic problems. Domain truncation by transparent boundary conditions for open problems where parabolic equation is utilized to govern wave propagation are in general computationally costly. For the deterministic problem, we utilize two approximations to a convolution-in-space type discrete boundary condition to reduce the cost, while maintaining accuracy in far range solutions. Perfectly matched layer adapted to the Crank-Nicolson finite difference scheme is also verified for a 2-D model problem, where implemented results and stability analyses for different approaches are compared. For the random problem, efficient moment calculation of electromagnetic propagation/scattering in various propagation environments is demonstrated, where the dimensionality of the random space varies from N = 2 to N = 100. Sparse grid collocation methods are used to obtain expected values and distributions, as a non-intrusive sampling method. Due to the low convergence rate in the sparse grid methods for moderate dimensionality and above, two different adaptive strategies are utilized in the sparse grid construction. These strategies are implemented in three different problems. Two problems are concerned with uncertainty in propagation domain intrinsic parameters, whereas the other problem has uncertainty in the boundary shape of the terrain, which is realized as the perfectly conducting (PEC) Earth surface.Publication A Non-Asymptotic Approach to the Analysis of Communication Networks: From Error Correcting Codes to Network Properties(2013-05) Eslami, AliThis dissertation has its focus on two different topics: 1. non-asymptotic analysis of polar codes as a new paradigm in error correcting codes with very promising features, and 2. network properties for wireless networks of practical size. In its first part, we investigate properties of polar codes that can be potentially useful in real-world applications. We start with analyzing the performance of finite-length polar codes over the binary erasure channel (BEC), while assuming belief propagation (BP) as the decoding method. We provide a stopping set analysis for the factor graph of polar codes, where we find the size of the minimum stopping set. Our analysis along with bit error rate (BER) simulations demonstrates that finite-length polar codes show superior error floor performance compared to the conventional capacity-approaching coding techniques. Motivated by good error floor performance, we introduce a modified version of BP decoding while employing a guessing algorithm to improve the BER performance. Each application may impose its own requirements on the code design. To be able to take full advantage of polar codes in practice, a fundamental question is which practical requirements are best served by polar codes. For example, we will see that polar codes are inherently well-suited for rate-compatible applications and they can provably achieve the capacity of time-varying channels with a simple rate-compatible design. This is in contrast to LDPC codes for which no provably universally capacity-achieving design is known except for the case of the erasure channel. This dissertation investigates different approaches to applications such as UEP, rate-compatible coding, and code design over parallel sub-channels (non-uniform error correction). Furthermore, we consider the idea of combining polar codes with other coding schemes, in order to take advantage of polar codes' best properties while avoiding their shortcomings. Particularly, we propose, and then analyze, a polar code-based concatenated scheme to be used in Optical Transport Networks (OTNs) as a potential real-world application The second part of the dissertation is devoted to the analysis of finite wireless networks as a fundamental problem in the area of wireless networking. We refer to networks as being finite when the number of nodes is less than a few hundred. Today, due to the vast amount of literature on large-scale wireless networks, we have a fair understanding of the asymptotic behavior of such networks. However, in real world we have to face finite networks for which the asymptotic results cease to be valid. Here we study a model of wireless networks, represented by random geometric graphs. In order to address a wide class of the network's properties, we study the threshold phenomena. Being extensively studied in the asymptotic case, the threshold phenomena occurs when a graph theoretic property (such as connectivity) of the network experiences rapid changes over a specific interval of the underlying parameter. Here, we find an upper bound for the threshold width of finite line networks represented by random geometric graphs. These bounds hold for all monotone properties of such networks. We then turn our attention to an important non-monotone characteristic of line networks which is the Medium Access (MAC) layer capacity, defined as the maximum number of possible concurrent transmissions. Towards this goal, we provide a linear time algorithm which finds a maximal set of concurrent non-interfering transmissions and further derive lower and upper bounds for the cardinality of the set. Using simulations, we show that these bounds serve as reasonable estimates for the actual value of the MAC-layer capacity.Publication Vehicular Ad Hoc Networks: Interplay of Geometry, Communications, and Traffic(2013-02) Nekoui, MohammadVehicular Ad Hoc Networks (VANETs) have been proposed to enhance the safety and efficiency of transportation systems. Such networks hold unique characteristics and fulfill new goals that necessitate their study from a whole new perspective other than what has been the prevailing paradigm for conventional Mobile Ad Hoc Networks (MANETs). The mission of this dissertation is to identify such unique characteristics and propose design strategies for VANETs that target the new system goals. We argue that the road and obstacle geometry are two important factors that should be appropriately addressed when studying the communications throughput of VANETs. To this end we first study the effect of traffic conditions and road geometry on VANET throughput scaling laws. We use graph-theoretic and geometrical concepts to derive the throughput scaling of single roads, downtown grids, and general geometry road systems. Moreover, since vehicular communications are supposed to operate in the high frequency ranges, line-of-sight between communicating vehicles picks up importance in VANETs. We use computational geometry tools to study how the specific geometry of obstacles (such as buildings) affects the capacity of urban area VANETs. Finally, the design goal in MANETs is mostly to enhance the communications metrics (such as throughput and/or delay) of the network, whereas in VANETs, is mainly to improve the safety and efficiency of commute. Yet, better performance in terms of the communications metrics does not necessarily lead into improved safety and efficiency of driving. To this end, the main theme of this dissertation is dedicated to the application-oriented design of VANETs for safety applications. To this end we bring the drivers’ application needs to the forefront of our attention and provide an analytic framework for VANET safety application design during both sparse and dense vehicular traffic conditions. We use tools from stochastic geometry to derive the optimal MAC parameters that satisfy the safety requirements of the system and validate our results through NS-2 simulations. Our ultimate goal there is to fill-in the current gap between purely traffic-based studies that fail to account for the non-idealities of communications, and communications-based ones which neglect the application needs of the system.Publication Nasics: A `Fabric-Centric' Approach Towards Integrated Nanosystems(2013-02) Narayanan, PritishThis dissertation addresses the fundamental problem of how to build computing systems for the nanoscale. With CMOS reaching fundamental limits, emerging nanomaterials such as semiconductor nanowires, carbon nanotubes, graphene etc. have been proposed as promising alternatives. However, nanoelectronics research has largely focused on a `device-first' mindset without adequately addressing system-level capabilities, challenges for integration and scalable assembly. In this dissertation, we propose to develop an integrated nano-fabric, (broadly defined as nanostructures/devices in conjunction with paradigms for assembly, inter-connection and circuit styles), as opposed to approaches that focus on MOSFET replacement devices as the ultimate goal. In the `fabric-centric' mindset, design choices at individual levels are made compatible with the fabric as a whole and minimize challenges for nanomanufacturing while achieving system-level benefits vs. scaled CMOS. We present semiconductor nanowire based nano-fabrics incorporating these fabric-centric principles called NASICs and N3ASICs and discuss how we have taken them from initial design to experimental prototype. Manufacturing challenges are mitigated through careful design choices at multiple levels of abstraction. Regular fabrics with limited customization mitigate overlay alignment requirements. Cross-nanowire FET devices and interconnect are assembled together as part of the uniform regular fabric without the need for arbitrary fine-grain interconnection at the nanoscale, routing or device sizing. Unconventional circuit styles are devised that are compatible with regular fabric layouts and eliminate the requirement for using complementary devices. Core fabric concepts are introduced and validated. Detailed analyses on device-circuit co-design and optimization, cascading, noise and parameter variation are presented. Benchmarking of nanowire processor designs vs. equivalent scaled 16nm CMOS shows up to 22X area, 30X power benefits at comparable performance, and with overlay precision that is achievable with present-day technology. Building on the extensive manufacturing-friendly fabric framework, we present recent experimental efforts and key milestones that have been attained towards realizing a proof-of-concept prototype at dimensions of 30nm and below.Publication Security Issues in Network Virtualization for the Future Internet(2012-09) Natarajan, SriramNetwork virtualization promises to play a dominant role in shaping the future Internet by overcoming the Internet ossification problem. Since a single protocol stack cannot accommodate the requirements of diverse application scenarios and network paradigms, it is evident that multiple networks should co-exist on the same network infrastructure. Network virtualization supports this feature by hosting multiple, diverse protocol suites on a shared network infrastructure. Each hosted virtual network instance can dynamically instantiate custom set of protocols and functionalities on the allocated resources (e.g., link bandwidth, CPU, memory) from the network substrate. As this technology matures, it is important to consider the security issues and develop efficient defense mechanisms against potential vulnerabilities in the network architecture. The architectural separation of network entities (i.e., network infrastructures, hosted virtual networks, and end-users) introduce set of attacks that are to some extent different from what can be observed in the current Internet. Each entity is driven by different objectives and hence it cannot be assumed that they always cooperate to ensure all aspects of the network operate correctly and securely. Instead, the network entities may behave in a non-cooperative or malicious way to gain benefits. This work proposes set of defense mechanisms that addresses the following challenges: 1) How can the network virtualization architecture ensure anonymity and user privacy (i.e., confidential packet forwarding functionality) when virtual networks are hosted on third-party network infrastructures?, and 2) With the introduction of flexibility in customizing the virtual network and the need for intrinsic security guarantees, can there be a virtual network instance that effectively prevents unauthorized network access by curbing the attack traffic close to the source and ensure only authorized traffic is transmitted?. To address the above challenges, this dissertation proposes multiple defense mechanisms. In a typical virtualized network, the network infrastructure and the virtual network are managed by different administrative entities that may not trust each other, raising the concern that any honest-but-curious network infrastructure provider may snoop on traffic sent by the hosted virtual networks. In such a scenario, the virtual network might hesitate to disclose operational information (e.g., source and destination addresses of network traffic, routing information, etc.) to the infrastructure provider. However, the network infrastructure does need sufficient information to perform packet forwarding. We present Encrypted IP (EncrIP), a protocol for encrypting IP addresses that hides information about the virtual network while still allowing packet forwarding with longest-prefix matching techniques that are implemented in commodity routers. Using probabilistic encryption, EncrIP can avoid that an observer can identify what traffic belongs to the same source-destination pairs. Our evaluation results show that EncrIP requires only a few MB of memory on the gateways where traffic enters and leaves the network infrastructure. In our prototype implementation of EncrIP on GENI, which uses standard IP header, the success probability of a statistical inference attack to identify packets belonging to the same session is less than 0.001%. Therefore, we believe EncrIP presents a practical solution for protecting privacy in virtualized networks. While virtualizing the infrastructure components introduces flexibility by reprogramming the protocol stack, it doesn't directly solve the security issues that are encountered in the current Internet. On the contrary, the architecture increases the chances of additive vulnerabilities, thereby increasing the attack space to exploit and launch several attacks. Therefore it is important to consider a virtual network instance that ensures only authorized traffic is transmitted and attack traffic is squelched as close to their source as possible. Network virtualization provides an opportunity to host a network that can guarantee such high-levels of security features thereby protecting both the end systems and the network infrastructure components (i.e., routers, switches, etc.). In this work, we introduce a virtual network instance using capabilities-based network which present a fundamental shift in the security design of network architectures. Instead of permitting the transmission of packets from any source to any destination, routers deny forwarding by default. For a successful transmission, packets need to positively identify themselves and their permissions to each router in the forwarding path. The proposed capabilities-based system uses packet credentials based on Bloom filters. This high-performance design of capabilities makes it feasible that traffic is verified on every router in the network and most attack traffic can be contained within a single hop. Our experimental evaluation confirm that less than one percent of attack traffic passes the first hop and the performance overhead can be as low as 6% for large file transfers. Next, to identify packet forwarding misbehaviors in network virtualization, a controller-based misbehavior detection system is discussed as part of the future work. Overall, this dissertation introduces novel security mechanisms that can be instantiated as inherent security features in the network architecture for the future Internet. The technical challenges in this dissertation involves solving problems from computer networking, network security, principles of protocol design, probability and random processes, and algorithms.Publication Robust and Scalable Domain Decomposition Methods for Electromagnetic Computations(2012-09) Paraschos, GeorgiosThe Finite Element Tearing and Interconnecting (FETI) and its variants are probably the most celebrated domain decomposition algorithms for partial differential equation (PDE) scientific computations. In electromagnetics, such methods have advanced research frontiers by enabling the full-wave analysis and design of finite phased array antennas, metamaterials, and other multiscale structures. Recently, closer scrutiny of these methods have revealed robustness and numerical scalability problems that prevent the most memory and time efficient variants of FETI from gaining widespread acceptance. This work introduces a new class of FETI methods and preconditioners that lead to exponential iterative convergence for a wide class of problems, are robust and numerically scalable. First, a two Lagrange multiplier (LM) variant of FETI with impedance transmission conditions, the FETI-2λ, is introduced to facilitate the symmetric treatment of non-conforming grids while avoiding matrix singularites that occur at the interior resonance frequencies of the domains. A thorough investigation on the approximability and stability of the Lagrange multiplier discrete space is carried over to identify the correct LM space basis. The resulting method, although accurate and flexible, exhibits unreliable iterative convergence. To accelerate the iterative convergence, the Locally Exact Algebraic Preconditioner (LEAP), which is responsible for improving the information transfer between neighboring domains is introduced. The LEAP was conceived by carefully studying the properties of the Dirichlet-to-Neumann (DtN) map that is involved in the sub-structuring process of FETI. LEAP proceeds in a hierarchical way and directly factorizes the signular and near-singular interactions of the DtN map that arise from domain-face, domain-edge and domain-vertex interactions. For problems with small number of domains LEAP results in scalable implementations with respect to the discretization. On problems with large domain numbers, the numerical scalability can only be obtained through ``global'' preconditioners that directly convey information to remotely separated domains at every DDM iteration. The proposed ``global" preconditiong stage is based on the new Multigrid FETI (MG-FETI) method. This method provides a coarse grid correction mechanism defined in the dual space. Macro-basis functions, that satisfy thecurl-curl equation on each interface are constructed to reduce the size of the coarse problem, while maintaining a good approximation of the characteristic field modes. Numerical results showcase the performance of the proposed method on one-way, 2D and 3D decomposed problems, with structured and unstructured partitioning, conforming and non-conforming interface triangulations. Finally, challenging, real life computational examples showcase the true potential of the method.Publication Power Efficient Continuous-Time Delta-Sigma Modulator Architectures for Wideband Analog to Digital Conversion(2012-05) Ranjbar, MohammadThis work presents novel continuous-time delta-sigma modulator architectures with low-power consumption and improved signal transfer functions which are suitable for wideband A/D conversion in wireless applications, e.g., 3G and 4G receivers. The research has explored two routes for improving the overall performance of continuous-time delta-sigma modulator. The first part of this work proposes the use of the power efficient Successive-Approximations (SAR) architecture, instead of the conventional Flash ADC, as the internal quantizer of the delta-sigma modulator. The SAR intrinsic latency has been addressed by means of a faster clock for the quantizer as well as full-period delay compensation. The use of SAR quantizer allows for increasing the resolution while reducing the total power consumption and complexity. A higher resolution quantizer, made feasible by the SAR, would allow implementing more aggressive noise shaping to facilitate wideband delta-sigma A/D conversion at lower over-sampling-rates. As proof of concept, a first-order CT delta-sigma modulator with a 5-bit SAR quantizer is designed and implemented in a 130 nm CMOS process which achieves 62 dB dynamic range over 1.92 MHz signal bandwidth meeting the requirements of the WCDMA standard. The prototype modulator draws 3.1 mW from a single 1.2 V supply and occupies 0.36 mm2 of die area. The second part of this research addresses the issue of out-of-band peaking in the signal-transfer-function (STF) of the widely used feedforward structure. The STF peaking is harmful to the performance of the modulator as it allows an interferer to saturate the quantizer and result in severe harmonic distortion and instability. As a remedy to this problem a general low-pass and peaking-free STF design methodology has been proposed which allows for implementing an all-pole filter in the input signal path for any given NTF. Based on the proposed method, the STF peaking of any feedforward modulator can be eliminated using extra feed-in paths to all the integrator inputs. A major drawback of the conventional feedforward topology having low-pass STF is the large sensitivity of the STF to the coefficients. In particular, component mismatch, due to random errors in the relative values of individual resistors or capacitors, can significantly degrade the anti-aliasing of the CT modulator and give rise to the unwanted STF peaking. To solve this problem two new architectures, namely dual-feedback and dual-feed-in are proposed which allow us to synthesize a low-pass STF with a smaller number of coefficients than the feedforward structure. The dual-feedback structure which shows significantly lower sensitivity to coefficient mismatch is extensively analyzed and simulated. Also for proof of concept a third-order modulator is implemented in a 130 nm CMOS process which achieves 76 dB dynamic-range over 5 MHz signal bandwidth meeting, for example, the requirements of a DVB-H receiver standard. In addition the modulator shows 77 dB anti-aliasing and less than 0.1 dB worst-case STF peaking. The measured power consumption of the modulator is 6 mW from a single 1.2 V and the die area is 0.56 mm2.Publication Security Issues in Networked Embedded Devices(2012-05) Chasaki, DanaiEmbedded devices are ubiquitous; they are present in various sectors of everyday life: smart homes, automobiles, health care, telephony, industrial automation, networking etc. Embedded systems are well known for their dependability, and that is one of the reasons that they are preferred over general purpose machines in various applications. Traditional embedded computing is changing nowadays mainly due to the increasing number of heterogeneous embedded devices that are, more often than not, interconnected. Security in the field of networked embedded systems is becoming particularly important, because: 1) Connected embedded devices can be attacked remotely. 2) They are resource constrained. This means, that due to their limited computational capabilities, a full-blown operating system that runs virus scanners and advanced intrusion detection techniques cannot be supported. The two facts lead us to the conclusion that a new set of vulnerabilities emerges in the networked embedded system area, which cannot be tackled using traditional security solutions. This work is focused on embedded systems that are used in the network domain. A very exciting instance of an embedded system that requires high performance, has limited processing resources and communicates with other embedded devises is a network processor (NP). Powerful network processors are central components of modern routers, which help them achieve flexibility and perform tasks with advanced processing requirements. In my work, I identified a new class of vulnerabilities specific to routers. The same set of vulnerabilities can apply to any other type of networked embedded device that is not traditionally programmable, but is gradually shifting towards programmability. Security in the networking field is a crucial concern. Many attacks in existing networks are based on security vulnerabilities in end-systems or in the end-to-end protocols that they use. Inside the network, most practical attacks have focused on the control plane where routing information and other control data are exchanged. With the emergence of router systems that use programmable embedded processors, the data plane of the network also becomes a potential target for attacks. This trend towards attacks on the forwarding component in router systems is likely to speed up in next-generation networks, where virtualization requires even higher levels of programmability in the data path.This dissertation demonstrates a real attack scenario on a programmable router and discusses how similar attacks can be realized. Specifically, we present an attack example that can launch a devastating denial-of-service attack by sending just a single packet. We show that vulnerable packet processing code can be exploited on a Click modular router as well as on a custom packet processor on the NetFPGA platform. Several defenses to target this specific type of attacks are presented, which are broadly applicable to a large scale of embedded devices. Security vulnerabilities can be addressed efficiently using hardware based extensions. For example, defense techniques based on processor monitoring can help in detecting and avoiding such attacks. We believe that this work is an important step at providing comprehensive security solutions that can protect the data path of current and future networks.Publication Accuracy of Biomass and Structure Estimates from Radar and Lidar(2012-05) Ahmed, Razi UddinA better understanding of ecosystem processes requires accurate estimates of forest biomass and structure on global scales. Recently, there have been demonstrations of the ability of remote sensing instruments, such as radar and lidar, for the estimation of forest parameters from spaceborne platforms in a consistent manner. These advances can be exploited for global forest biomass accounting and structure characterization, leading to a better understanding of the global carbon cycle. The popular techniques for estimation of forest parameters from radar instruments in particular, use backscatter intensity, interferometry and polarimetric interferometry. This dissertation analyzes the accuracy of biomass and structure estimates over temperate forests of the North-Eastern United States. An empirical approach is adopted, relying on ground truth data collected during field campaigns over the Harvard and Howland Forests in 2009. The accuracy of field biomass estimates, including the impact of the diameter-biomass allometry is characterized for the field sites. Full waveform lidar data from two LVIS field campaigns of 2009 over the Harvard and Howland forests is analyzed to assess the accuracy of various lidar-biomass relationships. Radar data from NASA JPL's UAVSAR is analyzed to assess the accuracy of the backscatter-biomass relationships with a theoretical radar error model. The relationship between field biomass and InSAR heights is explored using SRTM elevation and LVIS derived ground topography. Temporal decorrelation, a major factor affecting the accuracy of repeat-pass InSAR observations of forests is analyzed using the SIR-C single-day repeat data from 1994. Finally, PolInSAR inversion of heights over the Harvard and Howland forests is explored using UAVSAR repeat-pass data from the 2009 campaign. These heights are compared with LVIS height estimates and the impact of temporal decorrelation is assessed.Publication Clock Generation and Distribution for Enhancing Immunity to Power Supply Noise(2011-09) Jang, JinwookClock generation and distribution are getting difficult due to increased die size and increased number of cores in a microprocessor. Clock frequencies of microprocessors have been increased and expected to trend 4GHz in near future. This increased clock frequency requires to limit the clock skew and jitter to 5~10% of clock frequency, which is 12.5~25ps. On top of this, non-ideal power supply behavior (supply droops) is worsening available timing margin to the critical paths. This dissertation presents three types of interrelated works: 1) analytical modeling of period jitter of global clock distribution induced by power supply droop, 2) circuit design of a power supply droop detector with 20mV resolution and 1 cycle latency, and 3) architectural studies regarding new adaptive clocking architectures which reduce the worst case period jitter and the worst timing slack. In the analytical modeling of period jitter in global binary clock tree, period jitter caused by power supply droop is formulated into recursive expressions based on propagation delay variation expressions. These recursive expressions are simplified into non-recursive expressions to pinpoint the location of the worst case period jitter in time domain. During this process, the physical relationship between the power supply noise and period jitter is studied extensively in time domain. The resulted analytical expressions can predict the period jitter in the clock distribution with only 5 ps error compared to HSPICE simulations. [1] [2] [3]. The study of period jitter in global clock distribution showed that the input period jitter into the clock distribution can be adjusted to improve the period jitter at the end of the clock distribution. To achieve input jitter modulation, a very fast supply droop detector is vital. To address this challenge, a droop detector system is designed based on a detailed study on high end microprocessor power supply network. The study shows that the detector system can detect the supply noise with 20mV resolution in only one clock cycle latency. [4]. My two works are combined to study new adaptive clocking architectures. Two types of adaptive clocking architectures are studied and the results show both architectures can improve the worst case slack by 10ps. This can be considered a significant improvement when it is compared to the traditional worst case based clocking.Publication Low-profile, Modular, Ultra-Wideband Phased Arrays(2011-09) Holland, Steven SUltrawideband (UWB) phased antenna arrays are critical to the success of future multi-functional communication, sensing, and countermeasure systems, which will utilize a few UWB phased arrays in place of multiple antennas on a platform. The success of this new systems approach relies in part on the ability to manufacture and assemble low-cost UWB phased arrays with excellent radiation characteristics.This dissertation presents the theory and design of a new class of UWB arrays that is based on unbalanced fed tightly-coupled horizontal dipoles over a ground plane. Practical implementation of this concept leads to two inexpensive wideband array topologies, the Banyan Tree Antenna (BTA) Array, and the Planar Ultrawideband Modular Antenna (PUMA) Array. The key challenge in designing unbalanced-fed tightly-coupled dipole arrays lies in the control of a common mode resonance that destroys UWB performance. This work introduces a novel feeding strategy that eliminates this resonance and results in wideband, wide-angle radiation. More importantly, the new feeding scheme is simple and intuitive, and can be implemented at low-cost in both vertically and planarly-integrated phased array architectures. Another desirable byproduct of this topology is the electrical and mechanical modularity of the aperture, which enables easy manufacturability and assembly. A theoretical framework is presented for the new phased array topologies, which is then applied to the design of innite BTA and PUMA arrays that achieve 4:1 and 5:1 bandwidths,respectively. A practical application of this technology is demonstrated through the full design, fabrication, and measurement of a 7.25-21GHz 16x16 dual-pol PUMA array prototype for SATCOM applications.Publication Queue Length Based Pacing of Internet Traffic(2011-09) Yan, CaiAs the Internet evolves, there is a continued demand for high Internet bandwidth. This demand is driven partly by the widely spreading real-time video applications, such as on-line gaming, teleconference, high-definition video streaming. All-optical switches and routers have long been studied as a promising solution to the rapidly growing demand. Nevertheless, buffer sizes in all-optical switches and routers are very limited due to the challenges in manufacturing larger optical buffers. On the other hand, Internet traffic is bursty. The existence of burstiness in network traffic has been shown at all time scales, from tens of milliseconds to thousands of seconds. The widely existing burstiness has a very significant impact on the performance of small buffer networks, resulting in high packet drop probabilities and low link utilization. There have been many solutions proposed in the literature to solve the burstiness issue of network traffic. Traffic engineering techniques, such as traffic shaping and polishing, have been available in commercial routers/switches since the era of Asynchronous Transfer Mode (ATM) networks. Moreover, TCP pacing, as a natural solution to the TCP burstiness, has long been studied. Furthermore, several traffic conditioning and scheduling techniques are proposed to smooth core network traffics in a coordinated manner. However, all the existing solutions are inadequate to efficiently solve the burstiness issue of high-speed traffic. In this dissertation we aim to tackle the burstiness issue in small buffer networks, which refer to the future Internet core network consisting of all-optical routers and switches with small buffers. This dissertation is composed of two parts. In the first part, we analyze the impact of a general pacing scheme on the performance of a tandem queue network. This part serves as a theoretical foundation, based on which we demonstrate the benefits of pacing in a tandem queue model. Specifically, we use the Infinitesimal Perturbation Analysis (IPA) technique to study the impact of pacing on the instantaneous and average queue lengths of a series of nodes. Through theoretical analyses and extensive simulations, we show that under certain conditions there exists a linear relationship between system parameters and instantaneous/average queue lengths of nodes and that pacing improves the performance of the underlying tandem queue system by reducing the burstiness of the packet arrival process. In the second part, we propose a practical on-line packet pacing scheme, named Queue Length Based Pacing (QLBP). We analyze the impact of QLBP on the underlying network traffic in both time and frequency domains. We also present two implementation algorithms that allow us to evaluate the performance of QLBP in real experimental and virtual simulation environments. Through extensive simulations, we show that QLBP can effectively reduce the burstiness of network traffic and hence significantly improve the performance of a small buffer network. More important, the network traffic paced with QLBP does not exhibit a weakened competition capability when competing with non-paced traffic, which makes the QLBP scheme more attractive for ISPs.Publication Informativeness and the Computational Metrology of Collaborative Adaptive Sensor Systems(2011-05) Hopf, Anthony PComplex engineered systems evolve, with a tendency toward self-organization, which can, paradoxically, frustrate the aims of those seeking to develop them. The systems engineer, seeking to promote the development in the context of changing and uncertain requirements, is challenged by conceptual gaps that emerge within engineering projects, particularly as they scale up, that inhibit communication among the various stakeholders. Overall optimization, involving multiple criterion, is often expressed in the language of the individual parties, increasing the complexity of the overall situation, subsuming the participants within the evolution of the complex engineered system, containing the objective and subjective in counterproductive or inefficient ways that can arrest healthy development. The conventional pragmatic systems engineering approach to the resolution of such situations is to introduce architectural discipline by way of separation of concerns. In complex engineered systems projects, the crucial interface, at any level of abstraction, is between the technical domain experts and higher level decision makers. Bridging the ensuing conceptual gap requires models and methods that provide communication tools promoting a convergence of the conversation between these parties on a common "common sense" of the underlying reality of the evolving engineered system. In the interest of conceptual clarity, we confine our investigation to a restricted, but important general class of evolving engineered system, information gathering and utilizing systems. Such systems naturally resolve the underlying domain specific measures by reduction into common plausible information measures aimed at an overall sense of informativeness. For concreteness, we further restrict the investigation and the demonstration to a species that is well documented in the open literature: weather radar networks, and in particular to the case of the currently emerging system referred to as CASA. The multiobjective problem of objectively exploring the high dimensionality of the decision space is done using multiobjective genetic algorithms (MOGA), specifically the John Eddy genetic algorithms (JEGA), resulting in well-formed Pareto fronts and sets containing Pareto optimal points within 20% of the ideal point. A visualization technique ensures a clear separation of the subjective criterion provided by the decision makers by superficially adding preferences to the objective optimal solutions. To identify the integrative objective functions and test patterns utilized in the MOGA analysis, explorations of networked weather radar technologies and configuration are completed. The explorations identify trends within and between network topologies, and captures both the robustness and fragility of network based measurements. The information oriented measures of fusion accuracy and precision are used to evaluate pairs of networked weather radars against a standardized low order vortex test pattern, resulting in a metrics for characterizing the performance of dual-Doppler weather radar pairs. To define integrative measures, information oriented measures abstracting over sensor estimators and parameters used to estimate the radial velocity and returned signal from distributed targets, specifically precipitation, are shown to capture the single radar predicted performance against standardized test patterns. The methodology bridges the conceptual gap, based on plausible information oriented measures, standardized with test patterns, and objectively applied to a concrete case with high dimensionality, allowed the conversation to converge between the systems engineer, decision makers, and domain experts. The method is an informative objective process that can be generalized to enable expansion within the technology and to other information gathering and utilizing systems and sensor technologies.Publication Managing Lithographic Variations in Design, Reliability, and Test Using Statistical Techniques(2011-02) Sreedhar, AswinMuch of today's high performance computing engines and hand-held mobile devices are products of aggressive CMOS scaling. Technology scaling in semiconductor industry is mainly driven by corresponding improvements in optical lithography technology. Photolithography, the art used to create patterns on the wafer is at the heart of the semiconductor manufacturing process. Lately, improvements in optical technology have been difficult and slow. The transition to deep ultra-violet (DUV) light source (193nm) required changes in lens materials, mask blanks, light source and photoresist. It took more than ten years to develop a stable chemically amplified resist (CAR) for DUV. Consequently, as the industry moves towards manufacturing end-of-the-roadmap CMOS devices, lithography is still based on 193nm light source to print critical dimensions of 45nm, 32nm and likely 22nm. Sub-wavelength lithography creates a number of printability issues. The printed patterns are highly sensitive to topographic changes due to metal planarization, overlay errors, focus and dose variations, random particle defects to name a few. Design for Manufacturability methodologies came into being to help analyze and mitigate manufacturing impacts on the design. Although techniques such as Resolution Enhancement Techniques (RET) which involve optical proximity correction (OPC), phase shift masking (PSM), off-axis illumination (OAI) have been used to greatly improve the printability and better the manufacturing process window, they cannot perfectly compensate for these lithographic deficiencies. DFM methods were primarily devised to predict and correct systematic patterning problems that arise during manufacturing. Apart from systematic errors, random manufacturing variations may occur during photolithography. This is where a statistical approach to modeling of error behavior and its impact on different design parameters may prove to be effective. By incorporating statistical analysis to parameter variation, an effective, non-conservative design can be obtained. IC manufacturing yield is the foremost measure that determines the profitability of a given semiconductor manufacturing process. Thus early prediction of yield detractors is an important step in the design process. Such predictions are based on models, which in turn are rooted in manufacturing process. Success of yield prediction is based on quality of models. The models must capture physical phenomena and yet be efficient for computation. In this work, we present a lithography-based yield model that is computationally practical for use in the design process. The work also provides a methodology to perform statistical lithography rules check to identify hot spots in the design that can contribute to yield loss. Yield recovery methods aimed at minimally modifying the design ultimately produce more printable masks. Apart from IC manufacturing yield, ICs today are vulnerable to various reliability failures including electromigration (EM), negative bias temperature instability (NBTI), hot carrier injection (HCI) and electro-static discharge (ESD). Though such reliability issues have been examined since the beginning of CMOS, manufacturability impacts have created a renewed interest in analyzing them. In this dissertation, we introduce the concept of Design for reliable manufacturability (DFRM) to consider the effect of linewidth changes, gate oxide thickness variations and other manufacturing artifacts. A novel Litho-aware EM calibration and analysis has bee shown in this work. Results indicate that there is a significant difference in EM estimation when litho-predicted layouts are considered during analysis. DFM has always looked at linewidth and material thickness variation as detractors to the design. However, such variations are inevitable. In this work we also consider modeling sensitivity to variations to improve test pattern quality. Test structures sprinkled all over the wafer encounter varying process fluctuations. This can be harnessed to predict the current lithographic process corner which will later be used to choose the test pattern set that results in maximum fault coverage. In summary, the objective of this dissertation is to consider the impact of sub-wavelength lithography on printability and the overall impact on circuit reliability and manufacturing test development.Publication Band Structure Calculations of Strained Semiconductors Using Empirical Pseudopotential Theory(2011-02) Kim, JiseokElectronic band structure of various crystal orientations of relaxed and strained bulk, 1D and 2D confined semiconductors are investigated using nonlocal empirical pseudopotential method with spin-orbit interaction. For the bulk semiconductors, local and nonlocal pseudopotential parameters are obtained by fitting transport-relevant quantities, such as band gap, effective masses and deformation potentials, to available experimental data. A cubic-spline interpolation is used to extend local form factors to arbitrary q and the resulting transferable local pseudopotential V(q) with correct work function is used to investigate the 1D and 2D confined systems with supercell method. Quantum confinement, uniaxial and biaxial strain and crystal orientation effects of the band structure are investigated. Regarding the transport relavant quantities, we have found that the largest ballistic electron conductance occurs for compressively-strained large-diameter [001] wires while the smallest transport electron effective mass is found for larger-diameter [110] wires under tensile stress.Publication Low Cost Electronically Steered Phase Arrays for Weather Applications(2011-02) Sanchez-Barbetty, MauricioThe Electronically Steered Phased Array is one of the most versatile antennas used in radars applications. Some of the advantages of electronic steering are faster scan, no moving parts and higher reliability. However, the cost of phased arrays has always been prohibitive - in the order of $1M per square meter. The cost of a phased array is largely impacted by the cost of the high frequency electronics at each element and the cost of packaging. Advances in IC integration will allow incorporating multiple elements such as low noise amplifier, power amplifier, phase shifters and up/down-conversion into one or two ICs. Even though the cost for large quantities of ICs (both Silicon and GaAs) has lowered, the high cost of IC packaging and the array backplane still make the use of phase arrays for radar applications costly. The focus of this research is on techniques that reduce the packaging and the backplane cost of large electronically steered arrays. These techniques are based on simplified signal distributions schemes, reduction of layers in the backplane and use of inexpensive materials. Two architectures designed based on these techniques, as well as a novel BGA active antenna package for dual polarized phased arrays are presented. The first architecture, called the series fed row-column architecture, focuses on the reduction of phase shifters and control signals used in the backplane of the array. The second architecture, called the parallel plate feed architecture, is based on a simplified scheme for distribution of the local oscillator signal. A prototype making use of each one of these architectures is presented. Analysis of advantages and disadvantages of each of these architectures is described. The necessity of cost reduction is a factor that can possibly impact the polarization performance of the antenna. This factor is a motivation to study and develop calibration techniques that reduce the cross-polarization of electronically steered phased arrays. Advances on Interleaving Sparse Arrays, a beam forming technique for polarization improvement/correction in phased arrays, are also presented.