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Publication Secure and Energy Efficient Physical Unclonable Functions(2012-02) Srivathsa, SudheendraPhysical Unclonable Functions are a unique class of circuits that leverage the inherentvariations in manufacturing process to create unique,unclonableIDs and secret keys.The distinguishing feature of PUFs is that even an untrusted foundry cannot create a copy of the circuit as it is impossible to control the manufacturing process variations.PUFs can operate reliably in presence of voltage and temperature variations. In thisthesis, weexplorethe security offered by PUFs and tradeoffs between different metrics such as uniqueness, reliability and energy consumption.Benefits of sub-threshold PUF operation and the use of delay based Arbiter PUFs and ring oscillator PUFs in low power applications is evaluated. As we scale into lower technology nodes, there exists sufficient inter chip variation that enables each IC to be identified securely.The impact of scaling on the identification capabilities of a PUF and its reliability has been demonstrated in this work by analyzing the behavior of an Arbiter PUF in 45nm, 32nm and 22nm technology nodes. Further,the Arbiter PUF design has been implemented on a test-chip and fabricated using 45nm industry models andresults from post silicon validation are presented. Finally, we investigate a new class of PUF circuits in this work, that provide better security against machine learning based software modeling attacks. The strong identification capabilities and sufficiently high reliability offered by these PUF circuits make them promising candidates for future applications requiring securehardware cryptographic primitives.Publication Design and Testing of a Prototype High Speed Data Acquisition System for Nasa(2011-09) Vijayendra, Vishwas TumkurModern radar and signal processing applications require data acquisition systems capable of high-speed analog data reception and processing. These systems need to support sophisticated signal processing algorithms and reliable high-speed interfaces. The objective of this project is to develop a prototype of a state of the art data acquisition system to aid NASA’s Surface Water and Ocean Topography (SWOT) mission. The SWOT mission aims at monitoring water levels of various water bodies to predict and avoid any catastrophic events. The principal instrument is a Ka-band Radar Interferometer (KaRIN) that is used for the measurement of water levels. The collected data need to be digitized and processed using an FPGA based-data acquisition system housed in a satellite. The scope of this project involves the design, implementation and test of a high-speed printed circuit board (PCB) that serves as the prototype data acquisition system. A lot of emphasis is placed on layout design, as the PCB needs to support data rates up to three Giga samples per second. The goal of this research is to provide Jet Propulsion Laboratory (JPL), NASA with a prototype version of the high- speed acquisition system that can be integrated with the KaRIN system in future.Publication Automated Detection and Counting of Pedestrians on an Urban Roadside(2011-09) Prabhu, Gayatri DThis thesis implements an automated system that counts pedestrians with 85% accuracy. Two approaches have been considered and evaluated in terms of count accuracy, cost and ease of deployment. The first approach employs the Autoscope Solo Terra, a traffic camera which is widely used to monitor vehicular traffic. The Solo Terra supports an image processing-based detector that counts the number of objects crossing user-defined areas in the captured image. The count is updated based on the amount of movement across the selected regions. Therefore, a second approach has been considered that uses a histogram of oriented gradients (HoG), an advanced vision based algorithm proposed by Dalal et al. which distinguishes a pedestrian from a non-pedestrian based on an omega shape formed by the head and shoulders of a human being. The implemented detection software processes video frames that are streamed from a low-cost digital camera. The frames are divided into sub-regions which are scanned for an omega shape whenever movement is detected in those regions. It has been found that the HoG-based approach degrades in performance due to occlusion under dense pedestrian traffic conditions whereas the Solo Terra approach appears to be more robust. Undercounts and overcounts were encountered using the Solo Terra approach. To combat the disadvantages of both the approaches, they were integrated to form a single system where count is incremented predominantly using the Solo Terra. The HoG-based approach corrects the obtained count under certain conditions. A preliminary prototype of the integrated system has been verified.Publication Physical Information Theoretic Bounds on Energy Costs for Error Correction(2011-09) Ganesh, NateshWith diminishing returns in performance with scaling of traditional transistor devices, there is a growing need to understand and improve potential replacements technologies. Sufficient reliability has not been established in these devices and additional redundancy through use of fault tolerance and error correction codes are necessary. There is a price to pay in terms of energy and area, with this additional redundancy. It is of utmost importance to determine this energy cost and relate it to the increased reliability offered by the use of error correction codes. In this thesis, we have determined the lower bound for energy dissipation associated with error correction using a linear (n,k) block code. The bound obtained is implementation independent and is derived from fundamental considerations and it allows for quantum effects in the channel and decoder. We have also developed information theoretic efficacy measures that can quantify the performance of the error correction and their relationship to the corresponding energy cost.Publication Simulating a Universal Geocast Scheme for Vehicular Ad Hoc Networks(2011-05) Bovee, Benjamin LRecently a number of communications schemes have been proposed for Vehicular Ad hoc Networks (VANETs). One of these, the Universal Geocast Scheme (UGS) proposed by Hossein Pishro-Nik and Mohammad Nekoui, provides for a diverse variety of VANET-specific characteristics such as time-varying topology, protocol variation based on road congestion, and support for non line-of-sight communication. In this research, the UGS protocol is extended to consider inter-vehicle multi-hop connections in intersections with surrounding obstructions along with single-hop communications in an open road scenario. Since UGS is a probabilistic, repetition-based scheme, it supports the capacity-delay tradeoffs crucial for periodic safety message exchange. The approach is shown to support both vehicle-to-vehicle and vehicle-to-infrastructure communication. This research accurately evaluates this scheme using network (NS-2) and mobility (SUMO) simulators, verifying two crucial elements of successful VANETs, received packet ratio and message delay. A contemporary wireless radio propagation model is used to augment accuracy. Results show a 6% improvement in received packet ratio in intersection simulations combined with a decrease in average packet delay versus a previous, well-known inter-vehicle communication protocol.Publication Hardware Emulation of a Secure Passive Rfid Sensor System(2010) Todd, Michael GordonPassively powered radio frequency (RFID) tags are a class of devices powered via harvested ultra high frequency (UHF) radiation emitted by a reader device. Currently, these devices are relegated to little more than a form of wireless barcode, but could be used in a myriad of applications from simple product identification to more complex applications such as environmental sensing. Because these devices are intended for large scale deployment and due to the limited power that can be harvested from RF energy, hardware and cost constraints are extremely tight. The Electronic Product Code (EPC) Global Class 1 Generation 2 (Gen2) specification [EPC08] is currently the de facto communication standard for passively powered RFID. One issue restricting deployment and a cause for some privacy concerns is a lack of security in the Gen2 protocol. We will demonstrate a potential solution to this problem by using a novel block cipher designed for low power and area constrained devices to encrypt and transmit sensor data. This will be done while maintaining backward compatibility with the original standard and will require no substantial changes to the reader. Our solution will also provide one way authentication, data integrity checking and will provide security against replay attacks. In this thesis we will demonstrate an FPGA emulation of a Gen2 compatible RFID tag which will serve as a test bed for several novel features. We will leverage prior work involving several aspects of a tag [QL09] [PP07] as well as incorporate a novel low power encryption cipher [AB07] and external temperature sensor. Demonstrated in [CT08], FPGA emulation will allow for the independent verification of several components. This thesis will provide insight into the future of RFID and will provide insight into tag design as well as possible future updates to the Gen2 standard.Publication Low Cost Fpga Based Digital Beamforming Architecture for Casa Weather Radar Applications(2010) Seguin, Emmanuel JDigital beamforming is a powerful signal processing technique used in many communication and radar sensing applications. However, despite its many advantages, its high cost makes it a less popular choice than other directional antenna options. The development of a low cost architecture for digital beamforming would make it a more feasible option, allowing it to be used for a number of new applications. Specifically, the Collaborative, Adaptive Sensing of the Atmosphere (CASA) project’s Distributed Collaborative Adaptive Sensing (DCAS) system, a low cost weather radar system, could benefit from the incorporation of digital beamforming into small, inexpensive but highly functional radars. Existing DBF architectures are implemented in complex systems which include a number of expensive processing modules and other associated hardware. This project shows a low-cost digital beamforming architecture that has been developed by utilizing today’s powerful and inexpensive FPGA devices along with recently available low-voltage-differential-signaling enabled multi-channel analog to digital conversion hardware. The utilization of commercially available devices rather than custom hardware allows this architecture to be manufactured at a fraction of the cost of most. This makes it a viable alternative to the classic dish antennas for the DCAS system, allowing a reduction in size and cost which will benefit deployment. The flexibility of an FPGA-based DBF system will result in a more robust radar system. With this in mind, an architecture has been developed, fabricated and evaluated.Publication A Hardware Framework for Yield and Reliability Enhancement in Chip Multiprocessors(2009) Pan, AbhisekDevice reliability and manufacturability have emerged as dominant concerns in end-of-road CMOS devices. Today an increasing number of hardware failures are attributed to device reliability problems that cause partial system failure or shutdown. Also maintaining an acceptable manufacturing yield is seen as challenge because of smaller feature sizes, process variation, and reduced headroom for burn-in tests. In this project we investigate a hardware-based scheme for improving yield and reliability of a homogeneous chip multiprocessor (CMP). The proposed solution involves a hardware framework that enables us to utilize the redundancies inherent in a multi-core system to keep the system operational in face of partial failures due to hard faults (faults due to manufacturing defects or permanent faults developed during system lifetime). A micro-architectural modification allows a faulty core in a multiprocessor system to use another core as a coprocessor to service any instruction that the former cannot execute correctly by itself. This service is accessed to improve yield and reliability, but at the cost of some loss of performance. In order to quantify this loss we have used a cycle-accurate architectural simulator to simulate the performance of dual-core and quad-core systems with one or more cores sustaining partial failure. Simulation studies indicate that when a large and sparingly-used unit such as a floating point unit fails in a core, even for a floating point intensive benchmark, we can continue to run the faulty core with as little as 10% performance impact and minimal area overhead. Incorporating this recovery mechanism entails some modifications in the microprocessor micro-architecture. The modifications are also described here through a simplified model of a superscalar processor.Publication Information Theoretic Identification and Compensation of Nonlinear Devices(2009) Dolatshahi, SepidehBreaking the anonymity of different wireless users with the purpose of decreasing internet crime rates is addressed in this thesis by considering radiometric identification techniques. Minute imperfections and non-idealities in the different transmitter components, especially the inherent nonlinearity in power amplifiers, result in variations in their Volterra series representations which could be utilized as a signature. For a two user scenario, signal processing algorithms based on generalized likelihood ratio test(GLRT) and the classical likelihood ratio test are introduced and the resulting receiver decision rules and performance curves are presented. These algorithms consider the high signal to noise ratio(SNR) case where we have available the input samples completely at the receiver which is a practical assumption for most cases. Volterra series are widely used in behavioral modeling of power amplifiers. To validate the existence of these variations in the Volterra series representation of power amplifiers, process variations are introduced as major sources. The plausibility of our techniques are justified by deriving and comparing the Volterra coefficients for the fast and slow process corners. Finally,an information theoretic framework is presented where the amount of mutual information of the output about the Volterra coefficients represents the amount of anonymity taken from users. Here, some results for the low SNR case are presented to prove the achievability of some information about individual systems using our hardware anonymity breaking techniques.Publication A Process Variation Tolerant Self-Compensation Sense Amplifier Design(2008) Choudhary, AartiAs we move under the aegis of the Moore's law, we have to deal with its darker side with problems like leakage and short channel effects. Once we go beyond 45nm regime process variations also have emerged as a significant design concern.Embedded memories uses sense amplifier for fast sensing and typically, sense amplifiers uses pair of matched transistors in a positive feedback environment. A small difference in voltage level of applied input signals to these matched transistors is amplified and the resulting logic signals are latched. Intra die variation causes mismatch between the sense transistors that should ideally be identical structures. Yield loss due to device and process variations has never been so critical to cause failure in circuits. Due to growth in size of embedded SRAMs as well as usage of sense amplifier based signaling techniques, process variations in sense amplifiers leads to significant loss of yield for that we need to come up with process variation tolerant circuit styles and new devices. In this work impact of transistor mismatch due to process variations on sense amplifier is evaluated and this problem is stated. For the solution of the problem a novel self compensation scheme on sense amplifiers is presented on different technology nodes up to 32nm on conventional bulk MOSFET technology. Our results show that the self compensation technique in the conventional bulk MOSFET latch type sense amplifier not just gives improvement in the yield but also leads to improvement in performance for latch type sense amplifiers. Lithography related CD variations, fluctuations in dopant density, oxide thickness and parametric variations of devices are identified as a major challenge to the classical bulk type MOSFET. With the emerging nanoscale devices, SIA roadmap identifies FinFETs as a candidate for post-planar end-of-roadmap CMOS device. With current technology scaling issues and with conventional bulk type MOSFET on 32nm node our technique can easily be applied to Double Gate devices. In this work, we also develop the model of Double Gate MOSFET through 3D Device Simulator Damocles and TCAD simulator. We propose a FinFET based process variation tolerant sense amplifier design that exploits the back gate of FinFET devices for dynamic compensation against process variations. Results from statistical simulation show that the proposed dynamic compensation is highly effective in restoring yield at a level comparable to that of sense amplifiers without process variations. We created the 32nm double gate models generated from Damocles 3-D device simulations [25] and Taurus Device Simulator available commercially from Synopsys [47] and use them in the nominal latch type sense amplifier design and on the Independent Gate Self Compensation Sense Amplifier Design (IGSSA) to compare the yield and performance benefits of sense amplifier design on FinFET technology over the conventional bulk type CMOS based sense amplifier on 32nm technology node effective in restoring yield at a level comparable to that of sense amplifiers without process variations. We created the 32nm double gate models generated from Damocles 3-D device simulations [25] and Taurus Device Simulator available commercially from Synopsys [47] and use them in the nominal latch type sense amplifier design and on the Independent Gate Self Compensation Sense Amplifier Design (IGSSA) to compare the yield and performance benefits of sense amplifier design on FinFET technology over the conventional bulk type CMOS based sense amplifier on 32nm technology node.Publication Network Virtualization and Emulation using Docker, OpenvSwitch and Mininet-based Link Emulation(2020-09) Prabhu, NarendraWith the advent of virtualization and artificial intelligence, research on networked systems has progressed substantially. As the technology progresses, we expect a boom in not only the systems research but also in the network of systems domain. It is paramount that we understand and develop methodologies to connect and communicate among the plethora of devices and systems that exist today. One such area is mobile ad-hoc and space communication, which further complicates the task of networking due to myriad of environmental and physical conditions. Developing and testing such systems is an important step considering the large investment required to build such gigantic communication arrangements. We address two important aspects of network emulation in this work. We propose a network emulation framework, which emulates the functioning of a hierarchical software defined network. One such use-case is described using a mobile ad-hoc network (MANET) topology within a single system by leveraging contemporary network virtualization technologies. We present various aspects of the network, such as the dynamic communication in the software domain and provide a novel approach to build upon existing emulation techniques. The second part of the thesis presents a dynamic network link emulator. This emulator enables suitable link property re-configurations such as bandwidth, delay and packet loss for networked systems using simulation software. We characterize the results of tests for the link emulation using a hardware and software testbed. Through this thesis, we aim to make a small yet crucial contribution to the niche area of software defined networks.Publication Numerical Simulation of Thermoelectric Transport in Bulk and Nanostructured SiSn Alloys(2020-05) Dusetty, VenkatakrishnaThe current high demand for sustainable and renewable energy sources to solve world energy crisis has enormously increased interest in looking at alternative sources of energy. All the machines used in manufacturing process, electricity generation, residential applications, transportation etc., rejects energy in the form of heat into environment. Thermoelectric materials can convert thermal-to-electrical and electrical-to-thermal energy and can be utilized in waste-heat harvesting, more efficient cooling to reduce energy usage and CO2 emissions. Significant research efforts have been devoted over the past decade to thermoelectric materials, with particular emphasis being placed on combining materials selection with nanostructuring. The overarching goal was to reduce thermal conductivity through selective phonon scattering and thus boost the thermoelectric figure-of-merit (ZT). SiGe alloys, as well as superlattices and nanocomposites made from them, showed significant improvements upon nanostructuring and ZT exceeding one at high temperatures. Other group IV alloys were not studied in the context of thermoelectrics. However, SiSn alloys are widely studied for their optoelectronic properties because they were predicted to become direct-gap materials when Sn composition increased beyond about 50%. To address this gap, we study the thermoelectric properties of SiSn alloys. Furthermore, we develop an iterative full-band solver for the electron Boltzmann transport equation and use it to compute the electron and hole mobility and Seebeck coeffcient in SiSn alloys. The electronic structure of SiSn alloys was computed in the virtual crystal approximation from non-local empirical pseudopotentials, while the application of strain allowed us to extract the electron-phonon coupling deformation potentials for each alloy composition. We benchmark our code against available mobility data for Si and SiGe alloys and find that it accurately reproduces the measured values. Full phonon dispersion was computed from the adiabatic bond charge model, which was shown to accurately reproduce measured dispersion, and used in our phonon BTE solver to compute lattice thermal conductivities. Scattering rates include anharmonic phonon-phonon, impurity, isotope, alloy, and boundary mechanisms. The lowest thermal conductivity was obtained in SiSn alloys, which have been experimentally demonstrated with up to 18% Sn composition. This carries through when combined with calculations of electronic power factor, where mobilities and Seebeck coeffcients of SiSn alloys are comparable to those of SiGe. Furthermore, ZT is optimized through doping for every composition. The ZT improves dramatically at higher temperatures, reaching ZT of 1.9, 2.36 is obtained for Sn composition of 10% and 50% in a n-doped bulk SiSn alloys at a temperature of 1480 K. However, such high Sn composition of 50% is unlikely to be synthesized due to low solid solubility of Sn in Si. Lastly, we study the impact of nanostructuring in thin films on the ZT. We also establish the limits on how much the ZT can be improved through nanostructuring by studying thin films of SiSn alloys across temperature from room temperature up to 1500 K. We conclude that in bulk SiSn alloys, even at modest Sn concentration of 10%, ZT can reach 1.9, while in 20 nm thin films of n-type SiSn alloys, it can reach the long-sought target of ZT>3 and ZT of 2.16 is obtained in p-type nanostructured SiSn alloys.Publication SkinnySensor: Enabling Battery-Less Wearable Sensors Via Intrabody Power Transfer(2018-09) Kiran, NeevTremendousadvancement inultra-low powerelectronics and radiocommunica tionshas significantly contributed towards the fabrication of miniaturized biomedical sensors capable of capturing physiological data and transmitting them wirelessly. However, most of the wearable sensors require a battery for their operation. The battery serves as one of the critical bottlenecks to the development of novel wearable applications, as the limitations offered by batteries are affecting the development of new form-factors and longevity of wearable devices. In this work, we introduce a novel concept, namely Intra-Body Power Transfer (IBPT), to alleviate the limitations and problems associated with batteries, and enable wireless, batteryless wearable devices. The innovation of IBPT is to utilize the human body as the medium to transfer power to passive wearable devices, as opposed to employingon-boardbatteries for each individual device. The proposed platform eliminates the on-board rigid battery for ultra-low power and ultra-miniaturized sensors such that their form-factor can be flexible, ergonomically designed to be placed on small body parts. The platform also eliminates the need for battery maintenance (e.g., recharging or replacement) for multiple wearable devices other than the central power source. The performance of the developed system is tested and evaluated in comparison to traditional Radio Frequency based solutions that can be harmful to human interaction. The system developed is capable of harvesting on average 217µW at 0.43V and provides an average sleep/high impedance mode voltage of 4.5V.Publication Improvements to the UMASS S-Band FM-CW Vertical Wind Profiling Radar: System Performance and Data Analysis.(2018-05) Waldinger, JosephUpgrades to the University of Massachusetts S-Band FMCW boundary layer vertical wind profiling radar for use in the VORTEX-Southeast campaign are discussed. During the experiment, the radar characterizes velocity and reflectivity in clear-air and light to moderate precipitation conditions. Data is presented from the experiment which illustrates system performance and typical environmental results. This thesis begins with relevant background information on FM-CW radar operation, scattering mechanisms, and other calculations relevant to results discussed. The system hardware is described, along with improvements and modifications made prior to and during the experiment. Collected data is used to demonstrate system capabilities, improvements made, and remaining challenges. Various environmental features in the case of clear-air and precipitation are identified in the dataset. Several examples of Drop Size Distribution (DSD) estimates are presented, and the possibility of separating vertical wind speed biases from rain data is explored. Finally, the validity of results of DSD estimates are discussed.Publication Improving Efficiency of Thermoelectric Devices Made of Si-Ge, Si-Sn, Ge-Sn, and Si-Ge-Sn Binary and Ternary Alloys(2016-09) Khatami, Seyedeh NazaninThermoelectric devices with the ability to convert rejected heat into electricity are widely used in nowadays technology. Several studies have been done to improve the efficiency of these devices. However, because of the strong correlation between thermoelectric properties (electrical conductivity, Seebeck coefficient, and thermal conductivity including lattice and electron counterpart), improving ZT has always been a challenging task. In this study, thermal conductivity of group IV-based binary and ternary alloys such as SiGe, SiSn, GeSn, and SiGeSn has been studied. Phonon Boltzmann Transport Equation has been solved in the relaxation time approximation including intrinsic and extrinsic (in the presence of boundary and interfaces in the low-dimensional material) scattering mechanisms. Full phonon dispersion based on the Adiabatic Bond Charge model has been calculated for Si, Ge, and Sn. Virtual crystal approximation has been adapted to calculate the dispersion of SiGe, SiSn, GeSn, and SiGeSn. Two approaches have been introduced to reduce the lattice thermal conductivity of the materials under study. First, alloying results in a significant reduction of thermal conductivity. But, this reduction has been limited by the mass disorder scattering in the composition range of 0.2 to 0.8. Second, nanostructuring technique has been proposed to further reduce the thermal conductivity. Our study shows that, due to the atomic mass difference which gives rise to the elastic mass scattering mechanism, SiSn has the lowest thermal conductivity among the other materials under study. SiSn achieved the thermal conductivity of 1.18 W/mK at 10 nm at the Sn composition of 0.18, which is the experimentally stable state of SiSn. The results show that SiSn alloys have the lowest conductivity (3 W/mK) of all the bulk alloys, more than two times lower than SiGe, attributed to the larger difference in mass between the two constituents. In addition, this study demonstrates that thin films offer an additional reduction in thermal conductivity, reaching around 1 W/mK in 20 nm SiSn, GeSn, and ternary SiGeSn films, which is close to the conductivity of amorphous SiO$_2$. This value is lower than the thermal conductivity of SiGe at 10 nm which is 1.43 W/mK. Having lattice thermal conductivity reduced, electron transport has been studied by solving Boltzmann Transport Equation under low electric field including elastic and inelastic scattering mechanisms. Rode's iterative method has been applied to the model for obtaining perturbation of distribution function under a low electric field. This study shows that nanostructuring and alloying can reduce $\kappa_{ph}$ without significantly changing the other parameters. This is because of the phonon characteristics in solids in which MFP of phonons is much larger than those of electrons, which gives us the possibility of phonons confinement without altering electrons transport. Thermoelectric properties of SiGe in the bulk and nanostructure form have been studied to calculate ZT in a wide range of temperatures. The results demonstrate that ZT reaches the value of 1.9 and 1.58 at the temperatures of 1200 K and 1000 K respectively, with the Ge composition of 0.2 and carrier concentration of 5$\times$10$^{19}$ cm$^{-3}$ at 10 nm thickness. This model can be applied to SiSn and other binary and ternary alloys, to calculate the improved ZT. Hence, we conclude that group IV alloys containing Sn have the potential for high-efficiency TE energy conversion.Publication User Interface Design And Forensic Analysis For DIORAMA, Decision Support System For Mass Casualty Incidents(2015-09) Yi, JunIn this thesis we introduces the user interface design and forensic analysis tool for DIORAMA system. With an Android device, DIORAMA provides emergency personnel the ability to collect information in real time, track the resources and manage them. It allows the responders and commanders to mange multiple incidents simultaneously. This thesis also describes the implementations of commander app and responder app, as well as two different communication strategies used in DIORAMA. Several trials and simulated mass casualty incidents were conducted to test the functionalities and performance of DIORAMA system. All responders that participated in all trials were very satisfied with it. As a result, DIORAMA system significantly reduced the evacuation time by up to 43% when compared to paper based triage systems.Publication Development of Prototypes of a Portable Road Weather Information System(2015-09) Kainth, MehaWeather conditions have significant impact on road safety and roadway maintenance operations. Road Weather Information Systems (RWIS) play a significant role in providing weather and surface conditions to transportation agencies to monitor weather events. Fixed installations of RWIS are used for weather and pavement surface monitoring. However, permanent fixture installations may not be feasible due to reasons such as cost, accessibility to the site, siting concerns, and terrain. Portable RWIS provide a cost-effective solution in areas where permanent weather station installation is not possible. This study discusses use and benefits of the portable RWIS and outlines the issues involved in building them. This thesis presents the system design for building prototypes of two portable RWIS systems to be used by Massachusetts Department of Transportation (MassDOT). Portable RWIS consist of weather sensors and pavement sensors installed on a trailer-based platform and operate on solar power. The RWIS equipment mounted on trailers consists of non-invasive pavement sensors, wind sensor, precipitation sensor, atmospheric pressure sensor, humidity and dew point sensor and data logger to transmit data from the sensors to a central server. RWIS equipment from two different manufacturers have been selected. The two systems have been evaluated for their cost, operability, ease- of-use and deployability. A field study of two portable RWIS has been conducted to test accuracy of the data collected by these systems and the results have been evaluated. Characterizing the issues involved in developing such portable systems provide insights into situations where these systems may be most applicable.Publication Function Verification of Combinational Arithmetic Circuits(2015-05) Liu, DuoHardware design verification is the most challenging part in overall hardware design process. It is because design size and complexity are growing very fast while the requirement for performance is ever higher. Conventional simulation-based verification method cannot keep up with the rapid increase in the design size, since it is impossible to exhaustively test all input vectors of a complex design. An important part of hardware verification is combinational arithmetic circuit verification. It draws a lot of attention because flattening the design into bit-level, known as the bit-blasting problem, hinders the efficiency of many current formal techniques. The goal of this thesis is to introduce a robust and efficient formal verification method for combinational integer arithmetic circuit based on an in-depth analysis of recent advances in computer algebra. The method proposed here solves the verification problem at bit level, while avoiding bit-blasting problem. It also avoids the expensive Groebner basis computation, typically employed by symbolic computer algebra methods. The proposed method verifies the gate-level implementation of the design by representing the design components (logic gates and arithmetic modules) by polynomials in Z2n . It then transforms the polynomial representing the output bits (called “output signature”) into a unique polynomial in input signals (called “input signature”) using gate-level information of the design. The computed input signature is then compared with the reference input signature (golden model) to determine whether the circuit behaves as anticipated. If the reference input signature is not given, our method can be used to compute (or extract) the arithmetic function of the design by computing its input signature. Additional tools, based on canonical word-level design representations (such as TED or BMD) can be used to determine the function of the computed input signature represents. We demonstrate the applicability of the proposed method to arithmetic circuit verification on a large number of designs.Publication Indoor Navigation System for the Visually Impaired with User-centric Graph Representation and Vision Detection Assistance(2014-05) Dong, HaoIndependent navigation through unfamiliar indoor spaces is beset with barriers for the visually impaired. Hence, this issue impairs their independence, self-respect and self-reliance. In this thesis I will introduce a new indoor navigation system for the blind and visually impaired that is affordable for both the user and the building owners. Outdoor vehicle navigation technical challenges have been solved using location information provided by Global Positioning Systems (GPS) and maps using Geographical Information Systems (GIS). However, GPS and GIS information is not available for indoor environments making indoor navigation, a challenging technical problem. Moreover, the indoor navigation system needs to be developed with the blind user in mind, i.e., special care needs to be given to vision free user interface. In this project, I design and implement an indoor navigation application for the blind and visually impaired that uses RFID technology and Computer Vision for localization and a navigation map generated automatically based on environmental landmarks by simulating a user’s behavior. The focus of the indoor navigation system is no longer only on the indoor environment itself, but the way the blind users can experience it. This project will try this new idea in solving indoor navigation problems for blind and visually impaired users.Publication Internet Infrastructures for Large Scale Emulation with Efficient HW/SW Co-design(2021-09) Gula, Aiden KConnected systems are becoming more ingrained in our daily lives with the advent of cloud computing, the Internet of Things (IoT), and artificial intelligence. As technology progresses, we expect the number of networked systems to rise along with their complexity. As these systems become abstruse, it becomes paramount to understand their interactions and nuances. In particular, Mobile Ad hoc Networks (MANET) and swarm communication systems exhibit added complexity due to a multitude of environmental and physical conditions. Testing these types of systems is challenging and incurs high engineering and deployment costs. In this work, we propose a scalable MANET emulation framework using virtualized internet infrastructures that generalizes an assortment of application spaces with diverse attributes. We then quantify the architecture using various evaluation techniques to determine both feasibility and scalability. Finally, we developed a hardware offload engine for virtualized network systems that builds upon recent work in the field.