Off-campus UMass Amherst users: To download campus access dissertations, please use the following link to log into our proxy server with your UMass Amherst user name and password.

Non-UMass Amherst users: Please talk to your librarian about requesting this dissertation through interlibrary loan.

Dissertations that have an embargo placed on them will not be available to anyone until the embargo expires.

Author ORCID Identifier

https://orcid.org/0000-0002-0863-7167

AccessType

Open Access Dissertation

Document Type

dissertation

Degree Name

Doctor of Philosophy (PhD)

Degree Program

Electrical and Computer Engineering

Year Degree Awarded

2021

Month Degree Awarded

May

First Advisor

Jianhua (Joshua) Yang

Subject Categories

Electronic Devices and Semiconductor Manufacturing | Nanotechnology Fabrication

Abstract

Memristor or RRAM (Resistive Random Access Memory) based crossbar array architecture (CBA) is considered a leading contender for the next-generation non-volatile memory (NVM) as well as for future computing paradigms, such as in-memory computing, neuromorphic computing, neural networks, analog computing, reconfigurable computing, etc. Among many other attractive properties, memristors’ simple and dense 3D stackable structure is an essential enabler of these promising applications. However, the simplicity and high density of CBA comes at a price. CBA suffers from the so-called sneak path currents flowing through the unselected cells, which severely affects the read margin, makes CBA more power-hungry, increases the access time, and limits the maximum size of the array. All these problems could be tackled by using two-terminal and stackable bi-directional selector devices. Vertically integrating the memristor device with a two-terminal selector in a 1S1R (one selector one RRAM) crossbar array, memristor devices could realize their full scaling (2D) and stacking potential (3D). For a 1S1R integrated device to function properly, the memristor and selector should be compatible with their material composition and electrical properties. To realize low power and dense 1S1R array: a) the memristor device should have low energy operations, which will enable a low energy 1S1R cell as well as help the selector device to not wear-out prematurely; b) the matching selector device should have a high nonlinearity so that it can support a large 1S1R array operation. In this dissertation, I have designed and experimentally demonstrate a trilayer barrier-based tunneling selector, which will be engineered to show a very high nonlinearity, enabling a large 1S1R array operation. I also designed and fabricated few candidate memristor devices which meet the low energy requirements of the 1S1R integration. We choose a few promising switching material systems for such a demonstration, e.g., O- in YSZ, Ru+ in Ta2O5, Li+ in LLTO (Lithium Lanthanum Titanates). These material systems have a low activation energy of mobile ion diffusion in them, which should result in low energy operation if such material systems are used as a switching layer in memristor devices. To better understand the underlying fundamental mechanisms in these low-energy memristive devices, we will use the state of the art materials characterization techniques (e.g., STEM-EELS, TOF-SIMS, APT, etc.) to study the switching phenomena. We hope the results would open up an avenue to engineer memristors for 1S1R integration and dense arrays that can be used for non-volatile memory or neuromorphic computing.

DOI

https://doi.org/10.7275/22229081.0

Creative Commons License

Creative Commons Attribution 4.0 License
This work is licensed under a Creative Commons Attribution 4.0 License.

Download

Share

COinS