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Author ORCID Identifier

N/A

AccessType

Open Access Dissertation

Document Type

dissertation

Degree Name

Doctor of Engineering (DEng)

Degree Program

Electrical and Computer Engineering

Year Degree Awarded

2014

Month Degree Awarded

February

First Advisor

Maciej Ciesielski

Second Advisor

Sandip Kundu

Third Advisor

Michael Zink

Subject Categories

Computer and Systems Architecture | Digital Circuits | Hardware Systems | VLSI and Circuits, Embedded and Hardware Systems

Abstract

In the era of multi-core computing, the push for creating true parallel applications that can run on individual CPUs is on the rise. Application of parallel discrete event simulation (PDES) to hardware design verification looks promising, given the complexity of today’s hardware designs. Unfortunately, the challenges imposed by lack of inherent parallelism, suboptimal design partitioning, synchronization and communication overhead, and load balancing, render this approach largely ineffective. This thesis presents three techniques for accelerating simulation at three levels of abstraction namely, RTL, functional gate-level (zero-delay) and gate-level timing. We review contemporary solutions and then propose new ways of speeding up simulation at the three levels of abstraction. We demonstrate the effectiveness of the proposed approaches on several industrial hardware designs.

DOI

https://doi.org/10.7275/5382659

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