Design-specific path delay testing in lookup-table-based FPGAs
Publication Date
2005
Journal or Book Title
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
DOI
https://doi.org/10.1109/TCAD.2005.855955
Pages
867-877
Volume
25
Issue
5
Recommended Citation
Menon, PR; Xu, W; and Tessier, R, "Design-specific path delay testing in lookup-table-based FPGAs" (2005). IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. 1078.
https://doi.org/10.1109/TCAD.2005.855955
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