An architecture and compiler for scalable on-chip communication
Publication Date
2004
Journal or Book Title
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
DOI
https://doi.org/10.1109/TVLSI.2004.830919
Pages
711-726
Volume
12
Issue
7
Recommended Citation
Liang, H; Laffely, A; Srinivasan, S; and Tessier, R, "An architecture and compiler for scalable on-chip communication" (2004). IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 1083.
https://doi.org/10.1109/TVLSI.2004.830919
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