Impact of process variations on multi-level signaling for on-chip interconnects

Authors

V Venkatraman
W Burleson

Publication Date

2005

Journal or Book Title

18TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS

DOI

https://doi.org/10.1109/ICVD.2005.108

Pages

362-367

Book Series Title

International Conference on VLSI Design, Proceedings

Recommended Citation

Venkatraman, V and Burleson, W, "Impact of process variations on multi-level signaling for on-chip interconnects" (2005). 18TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS. 145.
https://doi.org/10.1109/ICVD.2005.108