Temporal Parallel Gate-level Timing Simulation
Publication Date
2008
Journal or Book Title
HLDVT: 2008 IEEE INTERNATIONAL HIGH LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS
DOI
https://doi.org/10.1109/HLDVT.2008.4695886
Pages
111-116
Book Series Title
IEEE International High Level Design, Validation and Test Workshop
Recommended Citation
Kim, D; Ciesielski, M; Shim, K; and Yang, S, "Temporal Parallel Gate-level Timing Simulation" (2008). HLDVT: 2008 IEEE INTERNATIONAL HIGH LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS. 194.
https://doi.org/10.1109/HLDVT.2008.4695886