Title
LAYER ASSIGNMENT FOR VLSI INTERCONNECT DELAY MINIMIZATION
Publication Date
1989
Journal or Book Title
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
DOI
https://doi.org/10.1109/43.31525
Pages
702-707
Volume
8
Issue
6
Recommended Citation
CIESIELSKI, MJ, "LAYER ASSIGNMENT FOR VLSI INTERCONNECT DELAY MINIMIZATION" (1989). IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS. 218.
https://doi.org/10.1109/43.31525
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