Technology mapping for reliability enhancement in logic synthesis
Publication Date
2005
Journal or Book Title
6th International Symposium on Quality Electronic Design, Proceedings
DOI
https://doi.org/10.1109/ISQED.2005.118
Pages
137-142
Recommended Citation
Wo, ZJ and Koren, I, "Technology mapping for reliability enhancement in logic synthesis" (2005). 6th International Symposium on Quality Electronic Design, Proceedings. 759.
https://doi.org/10.1109/ISQED.2005.118
COinS