DESIGNING INTERCONNECTION BUSES IN VLSI AND WSI FOR MAXIMUM YIELD AND MINIMUM DELAY
Publication Date
1988
Journal or Book Title
IEEE JOURNAL OF SOLID-STATE CIRCUITS
DOI
https://doi.org/10.1109/4.330
Pages
859-866
Volume
23
Issue
3
Recommended Citation
Koren, I; KOREN, Z; and PRADHAN, DK, "DESIGNING INTERCONNECTION BUSES IN VLSI AND WSI FOR MAXIMUM YIELD AND MINIMUM DELAY" (1988). IEEE JOURNAL OF SOLID-STATE CIRCUITS. 820.
https://doi.org/10.1109/4.330
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