A Study on Placement of Post Silicon Clock Tuning Buffers for Mitigating Impact of Process Variation
Publication Date
2009
Journal or Book Title
DATE: 2009 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3
DOI
https://doi.org/10.1109/DATE.2009.5090674
Pages
292-295
Book Series Title
Design, Automation and Test in Europe Conference and Expo
Recommended Citation
Nagaraj, K and Kundu, S, "A Study on Placement of Post Silicon Clock Tuning Buffers for Mitigating Impact of Process Variation" (2009). DATE: 2009 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION, VOLS 1-3. 890.
https://doi.org/10.1109/DATE.2009.5090674