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Thermal Transport Across 2D/3D Van Der Waals Interfaces

Designing improved field-effect-transistors (FETs) that are mass-producible and meet the fabrication standards set by legacy silicon CMOS manufacturing is required for pushing the microelectronics industry into further enhanced technological generations. Historically, the downscaling of feature sizes in FETs has enabled improved performance, reduced power consumption, and increased packing density in microelectronics for several decades. However, many are claiming Moore's law no longer applies as the era of silicon CMOS scaling potentially nears its end with designs approaching fundamental atomic-scale limits -- that is, the few- to sub-nanometer range. Ultrathin two-dimensional (2D) materials present a new paradigm of materials science and may pave the way for beyond-silicon CMOS technologies. Since the exfoliation of semi-metallic graphene in 2004, there have been discoveries of new families of semiconducting and insulating 2D materials that help realize fully-2D-based platforms, the study of novel quantum device physics, and provide new avenues in sensing and optical applications. However, selecting a new semiconducting channel material to design around is a highly non-trivial problem which requires finding a superlative candidate and then surrounding it with appropriate contacts (e.g., substrate) to ensure optimal performance. In modern microelectronics, a key feature for reliable performance is high interface thermal conductances so waste heat generated in device hot spots has a low-resistance pathway to thermal management hardware. Despite that importance, the study of interface thermal conductance between prospect 2D materials and their surrounding 3D contacts remains far behind the vast amount of literature covering their electrical and optical properties. This dissertation investigates interface thermal transport across mixed-dimensional 2D/3D van der Waals interfaces using a phonon Boltzmann transport model.
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