## Publication: Function Verification of Combinational Arithmetic Circuits

 dc.contributor.advisor Maciej Ciesielski dc.contributor.author Liu, Duo dc.contributor.department University of Massachusetts Amherst dc.contributor.department Electrical & Computer Engineering dc.date 2024-03-28T21:45:42.000 dc.date.accessioned 2024-04-26T18:16:43Z dc.date.available 2024-04-26T18:16:43Z dc.date.submitted May dc.date.submitted 2015 dc.description.abstract Hardware design verification is the most challenging part in overall hardware design process. It is because design size and complexity are growing very fast while the requirement for performance is ever higher. Conventional simulation-based verification method cannot keep up with the rapid increase in the design size, since it is impossible to exhaustively test all input vectors of a complex design. An important part of hardware verification is combinational arithmetic circuit verification. It draws a lot of attention because flattening the design into bit-level, known as the bit-blasting problem, hinders the efficiency of many current formal techniques. The goal of this thesis is to introduce a robust and efficient formal verification method for combinational integer arithmetic circuit based on an in-depth analysis of recent advances in computer algebra. The method proposed here solves the verification problem at bit level, while avoiding bit-blasting problem. It also avoids the expensive Groebner basis computation, typically employed by symbolic computer algebra methods. The proposed method verifies the gate-level implementation of the design by representing the design components (logic gates and arithmetic modules) by polynomials in Z2n . It then transforms the polynomial representing the output bits (called “output signature”) into a unique polynomial in input signals (called “input signature”) using gate-level information of the design. The computed input signature is then compared with the reference input signature (golden model) to determine whether the circuit behaves as anticipated. If the reference input signature is not given, our method can be used to compute (or extract) the arithmetic function of the design by computing its input signature. Additional tools, based on canonical word-level design representations (such as TED or BMD) can be used to determine the function of the computed input signature represents. We demonstrate the applicability of the proposed method to arithmetic circuit verification on a large number of designs. dc.description.degree Master of Science in Electrical and Computer Engineering (M.S.E.C.E.) dc.identifier.doi https://doi.org/10.7275/6948098 dc.identifier.orcid N/A dc.identifier.uri https://hdl.handle.net/20.500.14394/33227 dc.relation.url https://scholarworks.umass.edu/cgi/viewcontent.cgi?article=1210&context=masters_theses_2&unstamped=1 dc.source.status published dc.subject function verification dc.subject formal verification dc.subject CAD dc.subject Digital Circuits dc.subject Other Computer Engineering dc.subject VLSI and Circuits, Embedded and Hardware Systems dc.title Function Verification of Combinational Arithmetic Circuits dc.type openaccess dc.type article dc.type thesis digcom.contributor.author isAuthorOfPublication|email:duoliu@ecs.umass.edu|institution:University of Massachusetts Amherst|Liu, Duo digcom.identifier masters_theses_2/235 digcom.identifier.contextkey 6948098 digcom.identifier.submissionpath masters_theses_2/235 dspace.entity.type Publication
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