Neuromorphic computing algorithms and brain-inspired architectures hold promise to move beyond the current limitations of contemporary von Neumann architectures that are hindering current Artificial Intelligence (AI) implementations in terms of processing speeds and power consumption. The Cellular Neural Network (CeNN) is one such bio-inspired architecture that allows for massively parallel, analog computing schemes for high-speed image processing. The network is composed of simple, repeating processing elements referred to as cells and takes advantage of reprogrammable local connectivity for direct neighborhood interactions as well as propagating global dynamics to achieve a wide variety of applications. The first section will introduce the network fundamentals and underlying principles of network dynamics. Based off these fundamentals, a CeNN GUI software package with a digital twin simulator is written in python. The simulator is designed and tested for a wide variety of applications based off suggested hardware parameters. Simulated image and video processing approaching 100,000 frames per second are shown. Noisy image and video processing is also discussed, simulating the consequences of mismatch and variance in a fabricated network. Computational simulations for solving partial differential equations further demonstrate network robustness and capabilities. These digital twin simulations inform us on network performance and provide insight into the potential behavior of fabricated hardware networks. The second section focuses on the design and measurement of a prototype 5×5 hardware network based on pure CMOS using the TSMC 65nm process node. Edge detection and vertical/horizontal line detection algorithms are run demonstrating processing speeds greater than 20,000 frames per second. Performance merits are presented and compared to prior state of the art implementations. Finally, emerging Ta/HfOx drift memristor devices are introduced and the benefits of using such devices for neural networks (NN) are discussed. These two terminal devices are implemented into a “bridge synapse” architecture for efficient weight storage and intrinsic weight multiplication. A board-level CeNN prototype is built around these memristive devices and used to demonstrate horizontal line detection. This dissertation discusses and contributes to the development of massively parallel, low-power, analog NN hardware with a focus on CeNNs. The CeNN digital twin provides a means for easy network modelling in software and proof of concept. The fabrication of hardware and testing of a pure CMOS IC as well as the board-level memristor-based implementation further explore and demonstrate the feasibility of parallel, reprogrammable network architectures for high-speed, analog processing.