Advancements in artificial intelligence (AI) have driven remarkable performance across a wide range of applications. However, the increasing scale and complexity of AI algorithms have introduced significant challenges related to size, weight, power, and cost (SWaP+C) in conventional computing hardware, especially for edge intelligence applications where computing resources are limited. Analog in-memory computing (AIMC) hardware based on memristor devices offers a promising solution by enabling energy-efficient and parallel vector-matrix multiplication (VMM), a core operation in most AI models. As memristive technology evolves, from individual devices and crossbar arrays to integrated chips (IC) and multicore system-on-a-chip (SoC), a critical gap persists in bridging innovations across devices, peripheral circuits, architectures, algorithms, and applications to build energy-efficient and low-latency computing systems for edge intelligence. Addressing this challenge requires a hardware-software co-design approach: developing hardware that meet algorithm- and application-level requirements, while simultaneously optimizing algorithms to exploit the inherent characteristics of memristive hardware. In this dissertation, we adopt a hardware-software co-design approach to address challenges spanning peripheral circuit development, algorithm designs, and edge intelligence applications. We begin by developing a multichannel time-encoding testing system that integrates peripheral circuits and software modules for efficient characterization of memristive crossbar arrays with varying device stacks and array dimensions. This system enables time-domain VMM and supports rapid prototyping of neural network algorithms, thereby facilitating the development and evaluation of memristive crossbar arrays, which are subsequently integrated into a memristive SoC. Building on this foundation, we implement a hardware-algorithm co-design framework for hyperdimensional computing (HDC) using AIMC within the memristive SoC for language classification tasks. The co-design approach exploits the intrinsic randomness of memristor devices for data encoding and utilizes single-step analog VMM in memristive crossbar arrays to implement a single-layer perceptron (SLP). The memristive HDC achieves state-of-the-art performance in both simulation and hardware and demonstrates the energy efficiency of memristive hardware for edge intelligence. Additionally, we present optimization techniques that generalize the system for broader applications. Extending these co-design techniques, we implement a radiofrequency (RF) signal processing system on the memristive SoC. This system comprises signal processing components and neural networks for RF transmitter identification and anomaly detection. The system distributes RF signal spectrum analysis, demodulation, and multilayer perceptron inference across multiple memristive computing cores, enabling low-latency and energy-efficient RF signal processing. This advancement brings intelligence to the edge of wireless communication and lays the foundation for intelligent radio receivers. Finally, we further extend the memristive system to implement a cognitive radio receiver (CRR) by replacing conventional signal processing components with convolutional and fully connected neural networks. This CRR leverages the energy-efficient neural network models, accelerated by parallel analog VMMs implemented using memristive crossbar arrays within the SoC, to mitigate channel distortion and directly detect digital symbols from analog RF signals. This adaptive and energy-efficient signal processing solution, capable of direct data decoding on edge devices, marks a significant step toward intelligent and low-power wireless communication systems enabled by memristive hardware. The hardware-software co-design of memristive systems, including mixed-signal hardware development, signal processing and neural network algorithm optimization, and applications in language classification and wireless communications, paves the way to fully unlock the potential of AIMC hardware based on memristor devices for next-generation edge intelligence.