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CMOS COMPATIBLE MEMRISTOR NETWORKS FOR BRAIN-INSPIRED COMPUTING

Abstract
In the past decades, the computing capability has shown an exponential growth trend, which is observed as Moore’s law. However, this growth speed is slowing down in recent years mostly because the down-scaled size of transistors is approaching their physical limit. On the other hand, recent advances in software, especially in big data analysis and artificial intelligence, call for a break-through in computing hardware. The memristor, or the resistive switching device, is believed to be a potential building block of the future generation of integrated circuits. The underlying mechanism of this device is different from that of complementary metal-oxide-semiconductor (CMOS) transistors, which provides better scaling potential than that of CMOS transistors to make Moore’s law last longer. More importantly, inspired by the human brain, the computation based on memristor takes place in the exact location where data is stored, circumventing the need of data transfer between the separate computing and memory units in a conventional von-Neumann machine. There are still challenges to build memristor based machine to solve real-world applications. As an emerging device, despite promising properties demonstrated in single device level, it is still not mature enough to make integrated circuit chip with decent array performance, mostly due to large spatial and temporal variation. The problems may be solved in the future by the continuous device and material engineering, they can also be remedied with the help of the mature CMOS technology. In this dissertation, we present our experimental work of integrating memristors with CMOS circuitry. Firstly, we explore the possibility to use CMOS foundry compatible material (e.g. silicon oxide and hafnium oxide) to build memristors with performance satisfying the array operations. After that, we study the advanced memristor fabrication technology including three-dimensional stacking and foundry compatible integration with transistors. The maturity of the integrated memristor chip is then demonstrated by real-world applications, which include an ex-situ method to precisely calculate matrix multiplication for signal and image processing and an in-situ method to compensate defects and variability for the training of neural networks. The calculation based on this system suggests that, with integrated peripherals which will be available in the near future, the memristor-based system gains significant advantages over the conventional digital CMOS approaches in both speed and energy efficiency.
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