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Open Access Thesis
Electrical & Computer Engineering
Master of Science in Electrical and Computer Engineering (M.S.E.C.E.)
Year Degree Awarded
Month Degree Awarded
Chiplets have become an increasingly popular technology for extending Moore's Law and improving the reliability of integrated circuits. They do this by placing several small, interacting chips on an interposer rather than the traditional, single chip used for a device. Like any other type of integrated circuit, chiplets are in need of a physical layer of security to defend against hardware Trojans, counterfeiting, probing, and other methods of tampering and physical attacks.
Power distribution networks are ubiquitous across chiplet and monolithic ICs, and are essential to the function of the device. Thus, we propose a method of fingerprinting transient signals within the PDN to identify individual chiplet systems and physical-layer threats against these devices.
In this work, we describe a Python-wrapped HSPICE model we have built to automate testing of our proposed PDN fingerprinting methods. We also document the methods of analysis used- wavelet transforms and time-domain measurements- to identify unique characteristics in the voltage response signals to transient stimuli. We provide the true positive and false positive rates of these methods for a simulated lineup of chips across varying operating conditions to determine uniqueness and reliability of our techniques.
Our simulations show that, if characterized at varying supply voltage and temperature conditions in the factory, and the sensors used for identification meet the sample rates and voltage resolutions used in our tests, our protocol provides sufficient uniqueness and reliability to be enrolled. We recommend that experimentation be done to evaluate our methods in hardware and implement sensing techniques to meet the requirements shown in this work.
Burke, Matthew G., "Fingerprinting for Chiplet Architectures Using Power Distribution Network Transients" (2023). Masters Theses. 1330.