Phantom redundancy: A register transfer level technique for gracefully degradable data path synthesis

Karri, RIyer, BKoren, I2024-04-262024-04-262002-0110.1109/TCAD.2002.800450https://hdl.handle.net/20.500.14394/21479data path synthesis, graceful degradation, reconfigurable data paths, register transfer level, VLSI testing,Phantom redundancy: A register transfer level technique for gracefully degradable data path synthesisarticle