Testing and diagnosis of interconnect faults in cluster-based FPGA architectures

Harris, IGTessier, R2024-04-262024-04-262002-0110.1109/TCAD.2002.804108https://hdl.handle.net/20.500.14394/20791BIST, design for testability, interconnect, testing,Testing and diagnosis of interconnect faults in cluster-based FPGA architecturesarticle