Maciej CiesielskiAmeer Abdul Kader, Mohamed Basith Abdul2024-04-262011-08-192011-09910.7275/2175050https://hdl.handle.net/20.500.14394/47564This thesis describes an efficient method for speeding up functional verification of arithmetic circuits namely linear network such as wallace trees, counters using linear algebra techniques. The circuit is represented as a network of half adders, full adders and inverters, and modeled as a system of linear equations. The proof of functional correctness of the design is obtained by computing its algebraic signature using standard linear programming (LP) solver and comparing it with the reference signature provided by the designer. Initial experimental results and comparison with Satisfiability Modulo Theorem (SMT) solvers show that the method is efficient, scalable and applicable to complex arithmetic designs, including large multipliers. It is intended to provide a new front end theory/engine to enhance SMT solvers.Functional VerificationArithmetic CircuitsLinear AlgebraSMTArithmetic bit-levelEquivalence checkingElectrical and Computer Engineeringthesis