Tetris-XL: A Performance-Driven Spill Reduction Technique for Embedded VLIW Processors

Xu, WFTessier, R2024-04-262024-04-262009-01-01https://doi.org/10.1145/1582710.1582713https://hdl.handle.net/20.500.14394/20771Algorithms, Performance, Register pressure, instruction level parallelism, Very Long Instruction Word (VLIW) processor,Tetris-XL: A Performance-Driven Spill Reduction Technique for Embedded VLIW Processorsarticle