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Campus Access

Document Type


Degree Program

Electrical & Computer Engineering

Degree Type

Master of Science (M.S.)

Year Degree Awarded


Month Degree Awarded



Nanoprocessors, Defect Tolerance, Parameter Variation, FastTrack, NASIC, Simution Methodology


Nanoscale manufacturing techniques enable very high density nano fabrics but may cause orders of magnitude higher levels of defects and variability than in today‟s CMOS processes. As a result, nanoscale architectures typically introduce redundancy at multiple levels of abstractions to mask faults. Schemes such as Triple Modular Redundancy (TMR) and structural redundancies are tailored to maximize yield but can impact performance significantly. For example, due to increases in circuit fan-in and fan-out, a quadratic performance impact is often projected. In this thesis, we introduce a new class of redundancy schemes called FastTrack, designed to provide fault tolerance but without their negative impact on performance. FastTrack relies on combining non-uniform structural redundancy with uniquely biased nanoscale voters. A variety of such techniques are employed on a Wire Streaming Processor (WISP-0) implemented on the Nanoscale Application Specific Integrated Circuits (NASIC) nanowire fabric. We show that FastTrack schemes can provide 23% higher effective yield than conventional redundancy schemes even at 10% defect rates. Most importantly, the yield improvement is achieved in conjunction with 79% lesser performance impact at 10% defect rate. This is the first redundancy scheme we are aware of to achieve such degree of fault masking without the considerable performance impact of conventional approaches. The same setup is also used to mask the effects of parameter variation. FastTrack techniques show up to 6X performance improvement compared to more traditional redundancy schemes even at higher defect rates. In the absence of defects, a FastTrack scheme can be up to 7X faster than a traditional redundancy scheme.


First Advisor

Csaba Andras Moritz