Off-campus UMass Amherst users: To download campus access theses, please use the following link to log into our proxy server with your UMass Amherst user name and password.

Non-UMass Amherst users: Please talk to your librarian about requesting this thesis through interlibrary loan.

Theses that have an embargo placed on them will not be available to anyone until the embargo expires.

Document Type

Open Access

Degree Program

Electrical & Computer Engineering

Degree Type

Master of Science in Electrical and Computer Engineering (M.S.E.C.E.)

Year Degree Awarded

2011

Month Degree Awarded

May

Keywords

3D Integration, Prebond Testability, Delay Lock Loops, TSV Multiplexing

Abstract

The 3D integration of dies promises to address the problem of increased die size caused by the slowing of scaling. By partitioning a design among two or more dies and stacking them vertically, the average interconnect length is greatly decreased and thus power is reduced. Also, since smaller dies will have a higher yield, 3D integration will reduce manufacturing costs. However, this increase in yield can only be seen if manufactured dies can be tested before they are stacked. If not, the overall yield for the die stack will be worse than that of the single, larger die.

One of the largest issues with prebond die testing is that, to save power, a single die may not have a complete clock distribution network until bonding. This thesis addresses the problem of prebond die testability by ensuring the clock distribution network on a single die will operate with low skew during testing and at a reduced power consumption during operation as compared to a full clock network. The development of a Delay Lock Loop is detailed and used to synchronize disconnected clock networks on a prebond die. This succeeds in providing a test clock network that operates with a skew that is sufficiently close to the target postbond skew.

Additionally, a scheme to increase interdie bandwidth by multiplexing Through-Silicon Vias (TSVs) by the system clock is presented. This technique allows for great increase in the number of effective signal TSVs while imposing a negligible area overhead causing no performance degradation.

First Advisor

Sandip Kundu

Share

COinS