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Document Type

Open Access

Degree Program

Electrical & Computer Engineering

Degree Type

Master of Science in Electrical and Computer Engineering (M.S.E.C.E.)

Year Degree Awarded

2012

Month Degree Awarded

February

Keywords

Yield Analysis, Nanotechnology, NASIC, Nanowire

Abstract

Reliable and scalable manufacturing of nanofabrics entails significant challenges. Scalable nano-manufacturing approaches that employ the use of lithographic masks in conjunction with nanofabrication based on self-assembly have been proposed. A bottom-up fabrication of nanoelectronic circuits is expected to be subject to various defects and identifying the types of defects that may occur during each step of a manufacturing pathway is essential in any attempt to achieve reliable manufacturing. This thesis aims at analyzing the sources of defects in a nano-manufacturing flow and estimating the resulting yield loss. It integrates physical fabric considerations, manufacturing sequences and the resulting defect scenarios. This is in contrast to most current approaches that use conventional defect models and assume constant defect rates without analyzing the manufacturing pathway to determine the sources of defects and their probabilities. The manufacturing pathway will be analyzed for identifying the defects introduced during each manufacturing step in the sequence, followed by yield loss estimation.

First Advisor

Israel Koren

Second Advisor

C. Mani Krishna

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