Validating Cascading of Crossbar Circuits with an Integrated Device-Circuit Exploration
Publication Date
2009
Journal or Book Title
2009 IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES
DOI
https://doi.org/10.1109/NANOARCH.2009.5226357
Pages
37-42
Recommended Citation
Narayanan, P; Moritz, CA; Park, KW; and Chui, CO, "Validating Cascading of Crossbar Circuits with an Integrated Device-Circuit Exploration" (2009). 2009 IEEE/ACM INTERNATIONAL SYMPOSIUM ON NANOSCALE ARCHITECTURES. 1008.
https://doi.org/10.1109/NANOARCH.2009.5226357
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