"Temporal Parallel Gate-level Timing Simulation" by D Kim, M Ciesielski et al.

Electrical and Computer Engineering Faculty Publication Series

Temporal Parallel Gate-level Timing Simulation

D Kim
M Ciesielski
K Shim
S Yang

2008

111-116

HLDVT: 2008 IEEE INTERNATIONAL HIGH LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS

IEEE International High Level Design, Validation and Test Workshop

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