Off-campus UMass Amherst users: To download dissertations, please use the following link to log into our proxy server with your UMass Amherst user name and password.
Non-UMass Amherst users, please click the view more button below to purchase a copy of this dissertation from Proquest.
(Some titles may also be available free of charge in our Open Access Dissertation Collection, so please check there first.)
Static scheduling of multi domain circuits for functional verification
With the advent of System-On-a-Chip (SOC) design, many Application Specific Integrated Circuits (ASICs) now require multiple design clocks that operate asynchronously to each other. This design characteristic presents a significant challenge when these ASIC designs are mapped to hardware based verification systems such as parallel cycle-accurate simulators and logic emulators. In general, hardware based verification systems require all computation and communication to be synchronized to a global system clock. As a result, the undefined relationship between design asynchronous clocks can make it difficult to determine hold times for synchronous storage elements and causality relationships along reconvergent communication paths. This research presents new scheduling and synchronization techniques to support accurate mapping of designs with multiple asynchronous clocks to a hardware based logic emulator. The multi-domain scheduling problem can be divided into problems of scheduling multi-domain data paths, multi-domain clock paths, and multi-domain memories. Our approach is based upon a crucial observation that multi-domain functional requirements can be reduced to single domain constraints that need to be satisfied simultaneously. We have developed a new set of algorithms to statically schedule multi-domain circuits such that functional properties (timing closure, setup, and hold-time) are satisfied in each of the constituent domains. Through analysis, we show that our approach is scalable to an unlimited number of domains and supports increasingly large design sizes. To prove the effectiveness of our approach, we have integrated our algorithms into the compilation system for a commercial multi-FPGA logic emulation system. For three industrial designs mapped to a logic emulator using this software environment, modeling fidelity is improved and performance is enhanced versus previous manual mapping or hard-wired approaches. A theoretical analysis based on Rent's Rule validates the scalability of our approach as device sizes increase.
Kudlugi, Muralidhar R, "Static scheduling of multi domain circuits for functional verification" (2005). Doctoral Dissertations Available from Proquest. AAI3179893.