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Trace-based fault simulation methods
Abstract
Trace-based methods have been shown to be more effective than traditional fault simulation methods. The goal of this dissertation is to further accelerate trace-based fault simulation for combinational and synchronous sequential circuits. The use of general purpose shared memory multiprocessors for effective trace-based fault simulation is also investigated. Significant improvements in the speed of fault simulation of combinational circuits have been achieved by combining parallel pattern simulation of the fault-free circuit with tracing based methods for identifying detected faults. We present methods of achieving further speed improvements by reducing both the amount of backtracing within fanout-free regions and explicit fault simulation of stem faults. Results of simulating a set of benchmark combinational circuits with the proposed methods indicate that they are faster than other published methods, both with and without fault-dropping. We improve the speed of fault simulation of synchronous sequential circuits by using a linear iterative array model for such a circuit, and combining parallel fault simulation with surrogate fault simulation. Fault propagation of faults whose fault effects have not propagated from state variables in the previous time frame can be determined by backtracing from their surrogate lines and using the concept of surrogate faults. The others and surrogate faults need explicit forward propagation. Parallel fault simulation is used for the explicit forward propagation. Also, backtracing is extended to handle 0, 1, and X (unknown) signal values to represent unknown initial states of the sequential circuit. The results of simulating a set of benchmark sequential circuits show that execution time is reduced by 7 $\sim$ 54%, compared to a method which has been reported to be one of the fastest. Trace-based method is parallelized on a general-purpose multiprocessor with shared memory and the effect of the number of processors on speed-up of simulation and processor utilization is studied. The algorithm is based on a synchronous simulation method using a global simulation clock and task partitioning.
Subject Area
Electrical engineering|Computer science
Recommended Citation
Song, Ohyoung, "Trace-based fault simulation methods" (1992). Doctoral Dissertations Available from Proquest. AAI9219501.
https://scholarworks.umass.edu/dissertations/AAI9219501