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Testable designs for CMOS VLSI circuits
Abstract
Testing of Complementary Metal Oxide Semiconductor (scCMOS) circuits has become extremely important due to the emergence of scCMOS as a dominant technology for Very Large Scale integrated (scVLSI) circuits. The classical line stuck-at fault model is not adequate for modeling all physical faults in scCMOS circuits. One of such faults is Field Effect Transistor (scFET) stuck-open. Much work has been done on testing and testable designs for FET stuck-open faults in scCMOS combinational circuits. But very little has been reported on scCMOS sequential circuits. It is the objective of this research to investigate testable design techniques for scCMOS sequential circuits in which all stuck-open faults are detectable. Problems in detecting stuck-open faults in scCMOS sequential circuits are addressed and an in-depth research on testable realizations for stuck-open faults in scCMOS sequential circuit using new testing methodologies is presented. A testable design method of scCMOS sequential circuit for a given state table for stuck-open faults with standard scan-paths and the testing methodology, One-Scan/Two-Clock (1S/2C), has been investigated. The state of the second vector is generated by shifting-in the state of the first vector and applying primary input values using circuit under test itself. Necessary conditions for a stuck-open fault in scCMOS sequential circuit to be robustly testable with the testing methodologies, 1S/2C, and One-Scan/One-Clock (1S/1C), are shown. A 1S/1C testable stuck-open fault can be detected by shifting-in one state and applying two primary input values without clocking. Problems and testable designs for 1S/1C testing methodology in scCMOS complex gates, two-level scNAND-NAND, and scNAND-XOR realizations are presented. Testable designs for scCMOS sequential circuits without scan-paths have also been investigated. Two methods to obtain non-scan testable scCMOS sequential circuits are introduced. One adopts dynamic logic scCMOS circuits such as domino logic circuits and differential cascode voltage switch (scDCVS) logic circuits that are known to be easily testable for stuck-open faults using techniques presented for 1S/2C testable design. The other uses testable sequential machines synthesized for gate-level stuck-at faults and techniques developed for 1S/1C testable design.
Subject Area
Electrical engineering|Computer science
Recommended Citation
Park, Bong-Hee, "Testable designs for CMOS VLSI circuits" (1992). Doctoral Dissertations Available from Proquest. AAI9233127.
https://scholarworks.umass.edu/dissertations/AAI9233127