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Schemes to reduce test application time in digital circuit testing
Abstract
Test application time contributes significantly to the cost of VLSI testing. While it is essential to be able to perform test generation efficiently, it is also necessary to minimize the time spent in applying the tests to individual units. In this dissertation, we study the use of a hybrid scheme that combines scan testing and sequential testing in sequential circuits with full scan. The scheme exploits the finite state machine connectivity of the sequential machine in the test mode, thus avoiding time-consuming scan-in and scan-out. However, the scan facility is used both to detect faults that cannot be detected sequentially, as well as for faults for which efficient sequential test sequences cannot be found. Two algorithms for test generation in the hybrid scheme are described. Experimental results are reported for the stuck-at fault and the transition fault models. For the stuck-at fault model, the percentage reductions in test application time when compared to full scan is up to 87% in the ISCAS89 benchmark circuits. For the transition fault model, the percentage reductions fall between 21% and 82%. The hybrid test vectors generated under a stuck-at fault model also detect certain transition faults when applied at-speed. For the ISCAS89 circuits, the hybrid stuck-at test set is seen to achieve a transition fault coverage of between 52% to 91%. The hybrid test generation algorithm for sequential circuits with full scan can be applied to any fault model. However, for complex fault models such as the path delay fault model, the problem of reduction of test application time is important for combinational circuits as well. In this dissertation, a method to obtain compact test sets for path delay faults in combinational circuits is presented. Test set size is seen to decrease significantly using this approach thus reducing test application time. In summary, this dissertation examines the use of an alternative test application strategy for sequential circuits with full scan in order to reduce test application time. For combinational circuits, a method to derive smaller and more compact test sets has been presented for the path delay fault model.
Subject Area
Electrical engineering|Computer science
Recommended Citation
Saxena, Jayashree, "Schemes to reduce test application time in digital circuit testing" (1993). Doctoral Dissertations Available from Proquest. AAI9408341.
https://scholarworks.umass.edu/dissertations/AAI9408341