"DESIGNING INTERCONNECTION BUSES IN VLSI AND WSI FOR MAXIMUM YIELD AND " by I Koren, Z KOREN et al.

Electrical and Computer Engineering Faculty Publication Series

Title

DESIGNING INTERCONNECTION BUSES IN VLSI AND WSI FOR MAXIMUM YIELD AND MINIMUM DELAY

Authors

I Koren
Z KOREN
DK PRADHAN

Publication Date

1988

Journal or Book Title

IEEE JOURNAL OF SOLID-STATE CIRCUITS

DOI

https://doi.org/10.1109/4.330

Pages

859-866

Volume

Issue

Recommended Citation

Koren, I; KOREN, Z; and PRADHAN, DK, "DESIGNING INTERCONNECTION BUSES IN VLSI AND WSI FOR MAXIMUM YIELD AND MINIMUM DELAY" (1988). IEEE JOURNAL OF SOLID-STATE CIRCUITS. 820.
https://doi.org/10.1109/4.330

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