Current-sensed Interconnects: Static Power Reducation and Sensitivity to Temperature

Xu, Sheng

Publication:
Current-sensed Interconnects: Static Power Reducation and Sensitivity to Temperature

dc.contributor.advisor	Wayne P. Burleson
dc.contributor.author	Xu, Sheng
dc.contributor.department	University of Massachusetts Amherst
dc.contributor.department	Electrical & Computer Engineering
dc.date	2023-09-22T19:22:03.000
dc.date.accessioned	2024-04-26T21:11:59Z
dc.date.available	2024-04-26T21:11:59Z
dc.date.issued	2007-01-01
dc.date.submitted	2007-September
dc.description.abstract	Global on-chip interconnects in deep sub-micron CMOS present challenges in satisfying delay constraints in the presence of noise and dramatic temperature variations, while minimizing energy consumption due to leakage and static power. Although repeaters are typically used to reduce delay and maintain signal integrity in long interconnects, they introduce significant area, power (both dynamic and leakage), delay, noise and design overhead as well as exacerbating variations due to their local power supply noise and temperature. Current-Sensing is an alternative to repeaters that transfers signals with no intermediate circuits by sensing current rather than voltage at the end of a long interconnect. Among the current sensing circuits, Differential Current-Sensing (DCS), which uses conventional CMOS inverters to drive differential signal, is preferred because of its high common-mode noise rejection. The DCS circuit is fast and simple in layout compared to repeater insertion despite significant static and leakage power which remains a barrier for broad application. Temperature variation throughout the chip also causes the timing uncertainty on interconnects to increase. This thesis addresses current-sensing interconnect circuit design in several aspects. First, it provides an improved differential current-sensing circuit called the differential leakage-aware sense amplifier (DLASA), that uses local power gating that results in 39.6% reduced leakage and static power compared to conventional differential current sensing. Secondly, thermal impact on interconnect is studied and temperature sensitivity is analyzed for interconnect circuits. Theoretical analysis is discussed as a base design guideline, then accurate simulation based experiments in 65nm, 45nm and 32nm CMOS technologies are used for verification from 25OC to 150OC. Thus this project provides a view of the year of technology toward 2013.
dc.description.degree	Master of Science in Electrical and Computer Engineering (M.S.E.C.E.)
dc.identifier.doi	https://doi.org/10.7275/354653
dc.identifier.uri	https://hdl.handle.net/20.500.14394/47467
dc.relation.url	https://scholarworks.umass.edu/cgi/viewcontent.cgi?article=1092&context=theses&unstamped=1
dc.source.status	published
dc.subject	Electrical engineering
dc.subject	interconnect
dc.subject	circuit
dc.subject	VLSI
dc.subject	current sensing
dc.subject	power reduction
dc.subject	temperature
dc.title	Current-sensed Interconnects: Static Power Reducation and Sensitivity to Temperature
dc.type	open
dc.type	article
dc.type	thesis
digcom.contributor.author	isAuthorOfPublication\|email:shxu@ecs.umass.edu\|institution:University of Massachusetts Amherst\|Xu, Sheng
digcom.identifier	theses/57
digcom.identifier.contextkey	354653
digcom.identifier.submissionpath	theses/57
dspace.entity.type	Publication