Publication:
Post Silicon Clock Tuning System To Mitigate The Impact Of Process Variation On Performance

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dc.contributor.advisorSandip Kundu
dc.contributor.authorNagaraj, Kelageri
dc.contributor.departmentUniversity of Massachusetts Amherst
dc.contributor.departmentElectrical & Computer Engineering
dc.date2023-09-22T20:16:38.000
dc.date.accessioned2024-04-26T21:08:48Z
dc.date.available2009-09-25T00:00:00Z
dc.date.issued2010-01-01
dc.date.submitted2010-February
dc.description.abstractOptical shrink for process migration, manufacturing process variation and dynamic voltage control leads to clock skew as well as path delay variation in a manufactured chip. Since such variations are difficult to predict in pre-silicon phase, tunable clock buffers have been used in several microprocessor designs. The buffer delays are tuned to improve maximum operating clock frequency of a design. This however shifts the burden of finding tuning settings for individual clock buffers to the test process. In this project, we describe a process of using tester measurements to determine the settings of the tunable buffers for recovery of performance lost due to process variations. Then we study the impact of positioning of tunable buffers in the clock tree. In course of our study it was observed that the greatest benefit from tunable buffer placement can be derived, when the clock tree is synthesized with future tuning considerations. Accordingly, we present a clock tree synthesis procedure which offers very good mitigation against process variation, as borne out by the results. The results show that without any design intervention, an average improvement of 9% is achieved by our tuning system. However, when the clock tree is synthesized based on static timing information with tuning buffer placement considerations, much larger performance improvement is possible. In one example, performance improved by as much as 18%.
dc.description.degreeMaster of Science (M.S.)
dc.identifier.doihttps://doi.org/10.7275/1017260
dc.identifier.urihttps://hdl.handle.net/20.500.14394/47256
dc.relation.urlhttps://scholarworks.umass.edu/cgi/viewcontent.cgi?article=1455&context=theses&unstamped=1
dc.source.statuspublished
dc.subjectElectrical engineering
dc.subjectpost silicon tunable
dc.subjectprocess variation
dc.subjectcritical path tracing
dc.subjectdie specific tuning
dc.subjectclock tree synthesis
dc.subjectComputer and Systems Architecture
dc.subjectDigital Circuits
dc.subjectHardware Systems
dc.subjectComputer science
dc.titlePost Silicon Clock Tuning System To Mitigate The Impact Of Process Variation On Performance
dc.typeopen
dc.typearticle
dc.typethesis
digcom.contributor.authorisAuthorOfPublication|email:nagaraj.kelageri@gmail.com|institution:University of Massachusetts Amherst|Nagaraj, Kelageri
digcom.date.embargo2009-09-25T00:00:00-07:00
digcom.identifiertheses/378
digcom.identifier.contextkey1017260
digcom.identifier.submissionpaththeses/378
dspace.entity.typePublication
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