In the design of modern processors, thermal management has become one of the major challenges. Aggressive technology scaling and ever increasing demand for high performance VLSI circuits has resulted in higher current densities in the interconnect lines and increasingly higher power dissipation in the substrate. The importance of thermal effects on reliability and performance of integrated circuits increases as the technology advances. Thus a large number of thermal sensors are needed for accurate thermal mapping and thermal management. However, a rise in the number of the sensors might lead to large area cost and increase the complexity of routing. So to accurately calibrate the thermal gradients and reduce the area cost for thermal sensors, a systematic sensor distribution and allocation algorithm is essential. In this paper, we will first look into the existing thermal sensor placement techniques and add some further optimization technique to an existing temperature related algorithm. Then we will propose an algorithm based on the actual thermal gradient of the hotspots to determine the thermal sensor distribution on the microprocessors. The algorithm is designed to find the minimum number of sensors required and their correspondent locations while ensuring that all the calibrated temperatures’ deviation will be within a pre-determined error margin. We have used QT clustering algorithm to partition the hotspots and implemented a novel scheme for fast and efficient sensor location calculation. Our simulation is set on processor alpha21364, also known as EV6. Moreover, the anisotropic property of heat dissipation on chip is also considered. The final piece of this work will lead to some thermal management techniques on chip given the knowledge of the thermal sensor distribution. An optimized monitor network on chip (MNoC) scheme is set up for the non-uniform distributed sensors returned by the proposed thermal sensor placement algorithm. Two different schemes are proposed and analyzed to address this problem.